Abstract: An imaging system comprising a phase-detection image sensor comprising a plurality of phase-detection pixel units and a processor configured to: interpolate a green image to obtain a full resolution interpolated green image including defocused portions having artifacts and in-focus portions having sharp image, low-pass filter the full resolution interpolated green image to obtain a blurred image of the interpolated green image, combine the full resolution interpolated green image and the blurred image of the full resolution interpolated green image to obtain a corrected full resolution interpolated green image, where the artifacts of the defocused portions of the full resolution interpolated green image are removed, and the sharp image of the in-focus portions of the full resolution interpolated green image is unaffected.

Abstract: A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.

Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: An imaging system including a sensor wafer and a logic wafer. The sensor wafer includes a plurality of pixels arranged in rows and columns, the plurality of pixels arranged in rows and columns and including at least a first pixel and a second pixel positioned in a first row included in the rows. The sensor wafer includes a first transfer control line associated with the first row, the first transfer control line coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel. The logic wafer includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, a first storage control line coupled to a first storage gate associated with the first pixel and a second storage control line coupled to a second storage gate associated with the second pixel.

Abstract: A flare-blocking image sensor includes large pixels and small pixels, a microlens, and an opaque element. The large pixels and small pixels form a first and second pixel array respectively, each having a pixel pitch Px and Py. The second pixel array is offset from the first pixel array by ½Px and ½Py. A first large pixel of the large pixels is between and collinear with a first and a second small pixel separated by ?{square root over (Px2+Py2)} in a first direction and each having a width W less than both pixel pitch Px and Py. The microlens is aligned with the first large pixel. The opaque element is between the first large pixel and the microlens and extends, in the first direction, less than 1 2 ? ( P x 2 + P y 2 - W ) from the first small pixel toward the second small pixel. The opaque element has a width perpendicular to the first direction not exceeding width W.

Abstract: An image sensor comprises a plurality of high sensitivity photoelectric conversion elements, a plurality of low sensitivity photoelectric conversion elements, and a processor for processing signals read out from the plurality of low sensitivity photoelectric conversion elements and the plurality of high sensitivity photoelectric conversion elements, where the processor is configured to read out signals from the plurality of low-sensitivity photoelectric conversion elements multiple times in a single frame after multiple exposures and obtain a plurality of images of low-sensitivity in the single frame at different times.

Abstract: An image sensor has diffractive microlenses over pixels with central structures and ring(s) of material having index of refraction different from that of background material. Disposed beneath the diffractive microlenses are photodiodes that permit determining ratios of illumination of peripheral photodiodes to illumination of central photodiodes of the pixels, and, in embodiments, circuitry for determining said ratio. In embodiments, the ratio is used to find illumination wavelengths; and in other embodiments the ratio is used to determine focus of an imaging lens providing illumination. A method determines color by passing light through a diffractive lens disposed above photodiodes of the diffractive pixel and determining color from illumination peripheral and central photodiodes. An autofocus method of determining focus includes passing light through a diffractive lens and determining focus from illumination of peripheral photodiodes and central photodiodes of the pixel.

Abstract: An image sensor for imaging fingerprints has multiple photodiode groups each with field of view through a microlens determined by optical characteristics of the microlens and locations of the microlens and openings of upper and lower mask layers. Many photodiode groups have fields of view outwardly splayed from a center-direct field of view. A diameter of openings of the upper mask layer distant from the group having a center-direct field of view is larger than openings of a photodiode group having a center-direct field of view. A method of matching illumination of a group of photodiodes with center-direct field of view to illumination of photodiode groups having outwardly splayed fields of view includes sizing openings in the upper mask layer of photodiode groups with outwardly splayed fields of view larger than openings in the upper mask layer associated with photodiode groups having center-direct field of view.

Abstract: A dark-current-inhibiting image sensor includes a semiconductor substrate, a thin and a thin junction. The semiconductor substrate includes a front surface, a back surface opposite the front surface, a photodiode, and a concave surface between the front surface and the back surface. The concave surface extends from the back surface toward the front surface, and defines a trench that surrounds the photodiode in a cross-sectional plane parallel to the back surface. The thin junction extends from the concave surface into the semiconductor substrate, and is a region of the semiconductor substrate. The semiconductor substrate includes a first substrate region, located between the thin junction and the photodiode, that has a first conductive type. The photodiode and the thin junction have a second conductive type opposite the first conductive type.

Abstract: A novel method for driving a digital display having a plurality of pixel rows includes receiving a frame of data to be written to the display in a predetermined frame time, dividing the frame time into a plurality of time intervals, defining a plurality of row groups, and defining a unique sequence for each row group to display corresponding multi-bit data words and a number of off states on the pixels of the rows of the row groups. The drive sequence of each row is offset with respect to an initial row by a unique predetermined number of off states. The predetermined numbers of off states ensure that the pixel updates of the groups do not overlap.

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Abstract: A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

Abstract: In an embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including 12 green pixels, 2 blue pixels, and 2 red pixels, where a minimal repeating unit is immediately next to another minimal repeating unit in row and column directions. In another embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 8×8 pixels including 48 green pixels, 8 blue pixels, and 8 red pixels.

Abstract: An image sensor comprises an image sensor chip comprising a semiconductor substrate having a top surface and a plurality of microlenses disposed on the top surface; a cover glass having a first side in contact with air and a second side opposite to the first side; and a multi-layer structure disposed between the plurality of microlenses and the cover glass, which comprises: a bottom layer directly in contact with the plurality of microlenses, where the refractive index of the bottom layer is lower than the refractive index of the plurality of microlenses, and a top layer directly in contact with the second side of the cover glass, where the top layer is an optical glue made for bonding two optical elements.

Abstract: A cavity interposer has a cavity, first bondpads adapted to couple to a chip-type camera cube disposed within a base of the cavity at a first level, the first bondpads coupled through feedthroughs to second bondpads at a base of the interposer at a second level; and third bondpads adapted to couple to a light-emitting diode (LED), the third bondpads at a third level. The third bondpads coupled to fourth bondpads at the base of the interposer at the second level; and the second and fourth bondpads couple to conductors of a cable with the first, second, and third level different. An endoscope optical includes the cavity interposer an LED, and a chip-type camera cube electrically bonded to the first bondpads; the LED is bonded to the third bondpads; and a top of the chip-type camera cube and a top of the LED are at a same level.

Abstract: An image sensor includes a pixel array including at least one light-shielded area where no light enters and an imaging area where light enters, wherein each pixel includes a photoelectric conversion element, a black level processing unit that corrects an output of each pixel in the imaging area, and a memory that stores a predetermined black level reference for each pixel in the imaging area. The processing unit calculates a Slope, which is determined by an average output value at imaging of pixels in the at least one light-shielded area taken during imaging and a reference average output value of pixels in the at least one light-shielded area under certain conditions taken prior to imaging, and correct an output of each pixel in the imaging area using the predetermined black level reference and the Slope.

Abstract: A curved-surface image-sensor assembly has a porous carrier having a concave surface with a thinned image sensor bonded by an adhesive to its concave surface of the porous carrier; the porous carrier is mounted into a water-resistant package. The sensor assembly is made by fabricating a thinned, flexible, image-sensor integrated circuit (IC) and applying adhesive to a non-illuminated side of the IC; positioning the IC over a concave surface of a porous carrier; applying vacuum through the porous carrier to suck the IC onto the concave surface of the porous carrier; and curing the adhesive to bond the IC to the concave surface of the porous carrier.

Abstract: A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

Abstract: A stacked image sensor includes a signal-processing circuitry layer, a pixel-array substrate, a heat-transport layer, and a thermal via. The signal-processing circuitry layer includes a conductive pad exposed on a circuitry-layer bottom surface of the signal-processing circuitry layer. The pixel-array substrate includes a pixel array and is disposed on a circuitry-layer top surface of the signal-processing circuitry layer. The circuitry-layer top surface is between the circuitry-layer bottom surface and the pixel-array substrate. The heat-transport layer is located between the signal-processing circuitry layer and the pixel-array substrate. The thermal via thermally couples the heat-transport layer to the conductive pad.

Abstract: A failure detection circuit for an image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive a signal from a bitline of a bitline array in an image sensor that includes an array of pixels with each pixel is coupled to at least one bitline of the bitline array. The output stage is coupled to generate an output voltage indicative of any of the second input nodes being lower than the reference voltage.