Abstract: An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.

Abstract: An image sensor includes a photodiode disposed in a semiconductor material to generate image charge in response to incident light, and a floating diffusion disposed in the semiconductor material proximate to the photodiode. A transfer transistor is coupled to the photodiode to transfer the image charge from the photodiode into the floating diffusion in response to a transfer signal applied to a transfer gate of the transfer transistor. A source follower transistor is coupled to the floating diffusion to amplify a charge on the floating diffusion. The source follower transistor includes a gate electrode including a semiconductor material having a first dopant type; a source electrode, having a second dopant type, disposed in the semiconductor material; a drain electrode, having the second dopant type, disposed in the semiconductor material; and a channel, having the second dopant type, disposed between the source electrode and the drain electrode.

Abstract: An image sensor includes a semiconductor material including a plurality of photodiodes disposed in the semiconductor material. The image sensor also includes a first insulating material disposed proximate to a frontside of the semiconductor material, and an interconnect disposed in the first insulating material proximate to the frontside of the semiconductor material. A metal pad extends from a backside of the semiconductor material through the first insulating material and contacts the interconnect. A metal grid is disposed proximate to the backside of the semiconductor material, and the semiconductor material is disposed between the metal grid and the first insulating material disposed proximate to the frontside.

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams.

Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data.

Abstract: A time of flight pixel cell includes a photosensor to sense photons reflected from an object and pixel support circuitry. The pixel support circuitry includes charging control logic coupled to the photosensor to detect when the photosensor senses the photons reflected from the object. The pixel support circuitry also includes a controllable current source coupled to provide a charge current in response to a time of flight signal coupled to be received from the charging control logic. A capacitor is coupled to receive the charge current from the controllable current source in response to the time of flight signal, and voltage on the capacitor is representative of a round trip distance to the object. A counter circuit is coupled to the photosensor to count a number of the photons reflected from the object and received by the photosensor.

Abstract: A resonant-filter image sensor includes a pixel array including a plurality of pixels and a microresonator layer above the pixel array. The microresonator layer includes a plurality of microresonators formed of a first material with an extinction coefficient less than 0.02 at a free-space wavelength of five hundred nanometers. Each of the plurality of pixels may have at least one of the plurality of microresonators at least partially thereabove. The resonant-filter image sensor may further include a layer covering the microresonator layer that has a second refractive index less than a first refractive index, the first refractive index being the refractive index of the first material. Each microresonator may be one of a parallelepiped, a cylinder, a spheroid, and a sphere.

Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator.

Abstract: An athermal compound lens includes a plano-concave lens and a plano-convex lens. The plano-concave lens has a first focal length, a first refractive index n1, and planar object-side surface opposite a concave image-side surface. The plano-convex lens is axially aligned with the plano-concave lens and has (i) a second focal length, (ii) a second refractive index n2, (iii) a planar image-side surface, and (iv) a convex object-side surface between the planar image-side surface and the concave image-side surface. In a free-space wavelength range and temperature range: (a) the first focal length divided by the second focal length is less than ?0.68, and (b) first and second refractive indices n1 and n2 have respective temperature dependences ? ? ? n 1 ? ? ? T ? ? and ? ? ? ? ? n 2 ? ? ? T that satisfy ( ? ? ? n 1 ? ? ? T ) / ( ? ? ? n 2 ? ? ? T ) ? 2.

Abstract: An image sensor including a photodiode, a floating diffusion region, a first, second, and third doped region of a semiconductor material, and a first capacitor is presented. The photodiode is disposed in the semiconductor material to generate image charge in response to incident light. The floating diffusion region is disposed in the semiconductor material proximate to the photodiode. The floating diffusion region is at least partially surrounded by the first doped region of the semiconductor material. The second doped region and the third doped region of the semiconductor material each have an opposite polarity of the floating diffusion region and the first doped region. The floating diffusion region and at least part of the first doped region are laterally disposed between the second doped region and the third doped region.

Abstract: A method of image sensor fabrication includes forming a second semiconductor layer on a back side of a first semiconductor layer. The method also includes forming one or more groups of pixels disposed in a front side of the first semiconductor layer. The one or more groups of pixels include a first portion of pixels separated from the second semiconductor layer by a spacer region, and a second portion of pixels, where a first doped region of the second portion of pixels is in contact with the second semiconductor layer. Pinning wells are also formed and separate individual pixels in the one or more groups of pixels, and the pinning wells extend through the first semiconductor layer. Deep pinning wells are also formed and separate the one or more groups of pixels.

Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material, and a through-semiconductor-via coupled to a negative voltage source. Deep trench isolation structures are disposed between individual photodiodes in the plurality of photodiodes to electrically and optically isolate the individual photodiodes. The deep trench isolation structures include a conductive material coupled to the through-semiconductor-via, and a dielectric material disposed on sidewalls of the deep trench isolation structures between the semiconductor material and the conductive material.

Abstract: A method of backside illuminated image sensor fabrication includes forming a plurality of photodiodes in a semiconductor material, where the plurality of photodiodes are disposed to receive image light through a backside of the backside illuminated image sensor. The method further includes forming a transfer gate coupled to extract image charge from a photodiode in the plurality of photodiodes, and forming a storage gate coupled to the transfer gate to receive the image charge. Forming the storage gate includes forming an optical shield in the semiconductor material; depositing a gate electrode proximate to a frontside of the semiconductor material; and implanting a storage node in the semiconductor material, where the storage node is disposed in the semiconductor material between the optical shield and the gate electrode.

Abstract: An example apparatus for random sampling for horizontal noise reduction includes readout circuitry coupled to receive image data from an array of pixels, the readout circuitry including a plurality of sample and hold (S&H) circuits coupled to respective ones of a plurality of bitlines to sample and hold the image data in response to a plurality of S&H control signals, each of the plurality of S&H circuits including an S&H capacitor and an S&H switch. The S&H capacitor samples and holds respective image data, and the S&H switch coupled between a respective bitline and the respective S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals to open/close the S&H switch, where each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different time.

Abstract: A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.

Abstract: A dynamic random-access memory (DRAM) for use with a display includes a plurality of capacitive elements coupled to store one or more bits of data, and a plurality of switches where at least one individual switch in the plurality of switches is coupled to an individual capacitive element in the plurality of capacitive elements. A plurality of input/output (I/O) bit lines including 32 or more input/output bit lines is coupled to read out the data from the plurality of capacitive elements. A plurality of column select lines is coupled to enable readout of the plurality of capacitive elements.

Abstract: A chip-scale image sensor package includes a semiconductor substrate, a transparent substrate, a thin film, and a plurality of conductive pads. The semiconductor substrate has (i) a pixel array, and (ii) a peripheral region surrounding the pixel array. The transparent substrate covers the pixel array, has a bottom substrate surface proximate the pixel array, and a top substrate surface opposite the bottom substrate surface. The thin film is on a region of the top substrate surface directly above both (i) the entire pixel array and (ii) a portion of the peripheral region adjacent to the pixel array. Each of the plurality of conductive pads is located within the peripheral region, and is electrically connected to the pixel array. A portion of each of the plurality of conductive pads is not directly beneath the thin film.

Abstract: A method for fabricating a photosensor array integrated circuit includes forming an isolation trench by a method comprising depositing a hard mask layer on a [110]-oriented single-crystal silicon substrate wafer, depositing, exposing, and developing a photoresist on the hard mask layer to define photoresist openings of locations for the trenches, dry plasma etching through the photoresist openings to form openings in the hard mask layer of locations for the trenches, and performing an anisotropic wet etch through the openings in the hard mask layer. In particular embodiments, the trenches are lined with P-type silicon, a silicon dioxide dielectric, and an additional oxide layer before being filled with tungsten.

Abstract: A method of image sensor package fabrication includes forming a cavity in a ceramic substrate, and placing an image sensor in the cavity in the ceramic substrate. An image sensor processor is also placed in the cavity in the ceramic substrate, and the image sensor and the image sensor processor are wire bonded to electrical contacts. Glue is deposited on the ceramic substrate, and a glass layer is placed on the glue to adhere the glass layer to the ceramic substrate. The image sensor processor and the image sensor are disposed in the cavity between the glass layer and the ceramic substrate.