Abstract: A method includes receiving a layout; performing an optimization process to the layout to generate an optimized layout, wherein the optimization process comprising simulating a mask image of a photomask based on the layout; simulating an aerial image projected on a photoresist layer based on the mask image; simulating a resist image of the photoresist layer based on the aerial image; simulating an etch image of a layer underneath the photoresist layer based on the resist image; and performing an inverse lithographic technology (ILT) process to generate the optimized layout, wherein the ILT process is performed based on the mask image, the aerial image, the resist image, and the etch image; and fabricating a photomask based on the optimized layout.

Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

Abstract: Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a first die, a second die and a redistribution layer structure. The first die and the second die are disposed laterally. The redistribution layer structure is disposed over and electrically connected to the first die and the second die. The redistribution layer structure includes a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers. The redistribution layer structure further includes a first pad overlapped with the first die and a second pad overlapped with the second die. The first pad, the second pad and lines closest to the first die and the second die are located at substantially the same level, and from a top view, the first pad and the second pad have different shapes.

Abstract: A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: An interconnection structure includes a semiconductor substrate that is formed with a first metal trench and a second metal trench, a first metal via, a second metal via, a third metal trench and a fourth metal trench. The first metal via is disposed over and connected to the first metal trench. The second metal via is disposed over and connected to the second metal trench. The third metal trench is disposed over and connected to the first metal via. The fourth metal trench that is disposed over and connected to the second metal via. A thickness of the third metal trench is different from a thickness of the fourth metal trench.

Abstract: The present disclosure provides a semiconductor device and an operation method thereof, and a memory system. The semiconductor device includes a mode detection circuit and a charge pump. The mode detection circuit provides a first mode enable signal corresponding to a first state mode of the semiconductor device and provides a second mode enable signal corresponding to a second state mode of the semiconductor device. The charge pump operates in a first operation mode, in which a first output current is generated, based on the first mode enable signal, or operates in a second operation mode, in which a second output current is generated, based on the second mode enable signal. The first state mode includes an intra-word-line access state in which a continuous access is performed on memory cells on a same word line.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

Abstract: A casing for semiconductor packages that includes a plurality of press-fit pins is disclosed. Specific implementations include a shaft including a first end and a second end. The first end may include a head. The press-fit pin may include a bonding portion included at the second end. The bonding portion may include a first section extending substantially perpendicular from a longest length of the shaft. The bonding portion may also include an angled section coupled to a bonding foot. The bonding foot may be configured to be ultrasonically welded to a substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

Abstract: A light-emitting diode and a light-emitting device are provided. The light-emitting diode includes a semiconductor stack layer and a first electrode. The semiconductor stack layer has a light output surface and a back surface opposite to each other. On the back surface, the semiconductor stack layer has a first mesa exposing a first semiconductor layer thereof and a second mesa adjacent to the first mesa. The first electrode formed on the back surface of the semiconductor stack layer at least surrounds a portion of the second mesa, and the first electrode surrounding a portion of the second mesa extends toward the light output surface. The first electrode has a first chamfer portion, and the second mesa has a second chamfer portion. The first electrode and the second mesa have a minimum distance L, and a radius of curvature of the second chamfer portion is greater than or equal to ?{square root over (2)}L.

Abstract: A low-dropout (LDO) regulator and operation method thereof are provided. The LDO regulator may include a reference voltage generation circuit, an operational amplifier, a transistor and a multiphase configuration switching control circuit. The operation method may include: performing a first configuring operation to enable a first dedicated current path corresponding to a first phase to allow a target reference voltage used in LDO regulating mode to reach a first predetermined range after the first configuring operation is performed; performing a second configuring operation to enable a second dedicated current path corresponding to a second phase to allow the target reference voltage to reach a second predetermined range after the second configuring operation is performed; and performing a third configuring operation to allow the target reference voltage to be used as a reference voltage input into the operational amplifier in the LDO regulating mode after the third configuring operation is performed.

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Abstract: An anti-plasma coating formed on a surface of a component in a plasma chamber includes an insulation layer on the surface and a plasma-resistant layer on the insulation layer. The plasma-resistant layer includes one or more stacks, where each stack includes a crystalline layer and an amorphous layer. The anti-plasma coating improves a lifetime of the component in the plasma chamber with high-energy plasma sources.

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.