Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Abstract: A differential sensing system for sensing a current through a circuit element of a circuit, the differential sensing system comprising: a first current sense path having an input for coupling to a first node of the circuit element, the first current sense path comprising a first plurality of replica devices; a second current sense path having an input for coupling to a second node of the circuit element, the second current sense path comprising a second plurality of replica devices, wherein the second plurality is equal to the first plurality; a first cross-coupling switch operable to couple the input of the first current sense path to the second plurality of replica devices; a second cross-coupling switch operable to couple the input of the second current sense path to the first plurality of replica devices; differential amplifier circuitry having first and second inputs, wherein the differential amplifier circuitry is configured to output a differential replica current pair indicative of the current through

Abstract: A power module includes a substrate that includes an electrically insulating layer. A first electrically conducting region, a second electrically conducting region, and a third electrically conducting region are each disposed on the electrically insulative layer. The electrically conducting regions are electrically isolated from each other. A plurality of high-side power switches is disposed on and electrically coupled to the first electrically conducting region. A plurality of first connectors is coupled between the plurality of high-side power switches and the second electrically conductive region. A plurality of low-side power switches is disposed on and electrically coupled to the second electrically conductive region. A plurality of second connectors is coupled between the plurality of low-side power switches and the third electrically conductive region. A power lead is coupled to the first electrically conductive region via a spacer.

Abstract: A solid-state imaging device includes: a pixel including a photoelectric conversion element on a side of a first or light incident surface of a base; a pixel separation region surrounding a periphery of the pixel as viewed from a side of a second surface of the base; a transistor disposed on the side of the second surface of the base at a position corresponding to the pixel, the base having a periphery surrounded by the pixel separation region, the transistor having a direction of a gate length being oblique to the first direction or the second direction; and a FD region, a transfer gate electrode, or a base coupling section at the position corresponding to the pixel in a direction of a gate width of the transistor that is on the side of the second surface of the base, the transfer gate electrode being of a transfer transistor.

Abstract: A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

Abstract: A communication device includes: a receiving circuit, for receiving a data unit from a transmitter; a comparing circuit, coupled to the receiving circuit, for comparing a target station identity (STAID) with a STAID in the data unit, to generate a comparison result; a processing circuit, coupled to the comparing circuit, for performing a cyclic redundancy check (CRC) according to the comparison result and a check code in the data unit, to generate a check result, and for determining a frequency resource according to the check result and an extremely high throughput signal (EHT-SIG) field in the data unit; and a transmitting circuit, coupled to the processing circuit, for transmitting the frequency resource to a demodulation circuit.

Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.

Abstract: Disclosed are an optical coupling structure and a manufacturing method therefor. The optical coupling structure includes a first substrate, a plurality of light-source arrays disposed on a side of the first substrate, a second substrate, and a filtering layer disposed on a side of the second substrate. The first substrate is provided with a first through-hole penetrating through the first substrate, the first through-hole serves as a channel region and is preliminarily used for collecting optical signal emitted by each of the plurality of light-source array. The first substrate is disposed directly opposite to the filtering layer, the filtering layer is configured to filter light signals from different channel regions to reduce crosstalk of different wavelengths between adjacent channels. The second substrate is provided with a second through-hole to accommodate an end of an optical fiber, so that filtered optical signal may be transmitted to the fiber more accurately.

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Abstract: A method for diagnosing a condition of a first headset enclosed in a headset enclosure. The method comprises playing a first audio stimulus through a first speaker of the headset; detecting a first response signal derived by a first transducer; and determining a condition of the first speaker and/or first transducer based on the first response signal.

Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: The heat resistance of an organic semiconductor device including a step of forming an aluminum oxide film over and in contact with an organic semiconductor layer is improved. A heating step is performed after a layer containing an organometallic compound for a mask for an organic semiconductor layer, which is represented by General Formula (G1) below, is provided over the organic semiconductor layer. In General Formula (G1), Ar represents a substituted or unsubstituted aryl group having 6 to 30 carbon atoms or a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, X represents oxygen or sulfur, M represents a metal, n represents an integer greater than or equal to 1 and less than or equal to 5, and n is the same as the valence of the metal M. Note that when n is greater than or equal to 2, a plurality of Ars may be the same or different and Xs may be the same or different.

Abstract: An adaptive data rate method for use in a communication device. The communication device includes a controller and a transceiver coupled to each other. The method includes the controller increasing an initial data rate to generate a test data rate, and the transceiver transmitting a test packet according to the test data rate, a packet length of the test packet being less than a maximum packet length of a data packet. The method further includes the controller selecting one from the initial data rate and the test data rate as a selected data rate according to a transmission result of the test packet, and the transceiver transmitting the data packet according to the selected data rate.

Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

Abstract: A memory device including a memory array, a driver circuit, and a recover circuit is provided. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: The present disclosure relates to an electronic device that includes a first electronic component, a second electronic component, an interconnection structure below the first electronic component and the second electronic component and electrically connecting the first electronic component to the second electronic component, and a first waveguide below the first electronic component and the second electronic component and configured to transmit electromagnetic waves.

Abstract: In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.