Abstract: A chip includes a first circuit under test, a second circuit under test, and a clock masking circuit. The first circuit under test is coupled to the second circuit under test. The clock masking circuit includes a first clock control circuit, a second clock control circuit, and an enabling circuit. The first clock control circuit is configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal. The second clock control circuit is configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal. The enabling circuit is configured to provide a first enable signal for the first clock control circuit and a second enable signal for the second clock control circuit.

Abstract: An integrated circuit that performs testing of a circuit sub-block is described. This integrated circuit may include the circuit sub-block that performs a function, where the circuit sub-block is implemented in an analog domain using analog components and in a digital domain using digital components. Moreover, the integrated circuit may perform the testing of the circuit sub-block using independent testing of individual components in the circuit sub-block instead of testing the function of the circuit sub-block as a whole. Note that the individual components include the analog components and the digital components. In some embodiments, the testing may include functional safety testing.

Abstract: An illumination circuitry for a time-of-flight module for switching at least two illuminators, wherein the illumination circuitry is configured to: receive an input illumination signal from a time-of-flight sensor; and generate, based on the input illumination signal, synchronized first illumination signals for a first illuminator and second illumination signals for a second illuminator.

Abstract: A display panel is provided, including a touch layer including a plurality of touch electrodes; a plurality of touch wires, wherein each of the touch wires is connected to one touch electrode respectively to transmit touch signals of the touch electrodes; and a plurality of conductive wire segments, wherein each of the conductive wire segments and the touch electrodes are in parallel connection. By adding impedance of parallel connection to each of the touch electrodes, voltage drop incurred by the common electrodes and the conductive wire segments is reduced, and the stability of the common voltage signal transmitted in the display region of the display panel is improved.

Abstract: A sensor device includes: multiple pixel circuits each of which includes a light receiver and generates an event signal corresponding to presence or absence of an event in accordance with a light reception result of the light receiver; and a pre-processing circuit that generates processing information on the basis of the multiple event signals, and supplies the processing information to a processing circuit including a neural network. The pre-processing circuit includes: a first weighted addition circuit that performs a weighted addition process on the basis of two or more of the event signals generated by respective two or more pixel circuits among the multiple pixel circuits; and a first determination circuit that generates a first feature value signal on the basis of a result of the weighted addition process in the first weighted addition circuit. The pre-processing circuit generates processing information based on the first feature value signal.

Abstract: Sensor methods and systems incorporating an integrated illumination or light source are provided. The sensor can include a plurality of pixels and the integrated light source. The sensor can additionally include or be associated with imaging optics. The light source operates to generate illumination light that is passed through the imaging optics towards a scene within a field of view of the sensor system. Objects within the field of view reflect light that is collected by the imaging optics and passed to at least some of the pixels. In at least some configurations, an output of the light source is located adjacent the pixels, and provides the illumination light to the imaging optics by reflecting the illumination light from at least some of the pixels. In other configurations, the light source excites pixel elements, which then produce illumination light that is provided to the imaging optics.

Abstract: A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.

Abstract: The present disclosure discloses a pixel driving circuit and a control method thereof. The pixel driving circuit includes: a signal driving module for driving a light emitting diode to emit light based on connected scanning signal lines and data signal lines; a voltage detection module connected to the signal driving module for collecting a detection voltage of the light emitting diode and comparing the detection voltage with a reference voltage to generate a control signal; and a short circuit processing module connected to the signal driving module and the voltage detection module for controlling the light emitting diode based on the control signal.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a channel layer, a barrier layer and a P-type semiconductor layer stacked sequentially. The barrier layer includes a first region and an oxygen-doped region, an oxygen concentration of the oxygen-doped region is higher than that of the first region, and a projection of the oxygen-doped region on the substrate at least partially overlaps with a projection of the P-type semiconductor layer on the substrate. When the semiconductor device is in an off state, 2DEG may be depleted to obtain an enhancement-mode device, and the oxygen-doped region with a larger unit cell parameter and a wider band gap is obtained by performing an oxygen doping process. Under an electric field, an energy band between the barrier layer and the P-type semiconductor bends more, which increases a barrier height, reduces leakage current, and improves power characteristics.

Abstract: The present disclosure provides a display panel, the display panel includes a substrate, a light-emitting layer, a first refractive layer, and a second refractive layer. The first refractive layer is arranged on a side of the light-emitting layer away from the substrate. The second refractive layer covers a side of the first refractive layer away from the substrate and fills a plurality of openings of the first refractive layer. The second refractive layer extends from a display area to a non-display area and covers a bending area to protect wirings in the bending area, and the second refractive layer may replace a protective glue layer in prior art, which is beneficial to saving processes.

Abstract: A semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. The redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. The first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. The second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. The first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. The encapsulated die is disposed below the first side of the first conductive via.

Abstract: Apparatus and associated methods relate to a post temperature calibration translation circuit (PTCTC) configured to generate a signal corresponding to a predetermined temperature voltage translation relationship (TVTR). In an illustrative example, the PTCTC may be coupled to a motor controller including a control logic to regulate a power input to a motor based on the TVTR. The PTCTC further includes an input port configured to receive a temperature sensor output based on a predetermined transfer function. At least one analog corrective translation circuit (ACTC), for example, may generate temperature input signals to the motor power controller based on the temperature sensor output. The temperature input signals are generated based on a calibrated transfer function such that the temperature input signals substantially match an output according to the TVTR. Various embodiments may advantageously avoid modification of the control logic when the predetermined transfer function is altered.

Abstract: A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an n-type semiconductor layer, a functional layer, a p-type semiconductor layer, a first AlN layer and a first heavily doped n-type semiconductor layer arranged in sequence. The first AlN layer is provided to reduce the diffusion of p-type ions from the p-type semiconductor layer into the first heavily doped n-type semiconductor layer, to avoid a thicker tunneling junction caused by n-type ions/p-type ions co-doping, to improve the tunneling effect of carriers, to enhance the uniformity of the current density distribution of the first heavily doped n-type semiconductor layer injected into the p-type semiconductor layer, to solve the problem that the p-type semiconductor layer has low carrier mobility and high resistivity.

Abstract: An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.

Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

Abstract: A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.

Abstract: Provided are a semiconductor device configured to suppress a temperature rise of a semiconductor element and to suppress warpage, a method for manufacturing the semiconductor device including a cooling medium sealing step, and an electronic apparatus including the semiconductor device. The semiconductor device includes: a semiconductor element; a substrate to which the semiconductor element is adhered; and a cooling medium with which a clearance formed when the semiconductor element and the substrate are adhered to each other with an adhesive is filled. The cooling medium is a liquid metal, a metal-coated small sphere, or a liquid metal and a metal-coated small sphere. The cooling medium transmits heat generated by the semiconductor element to the outside to suppress a temperature rise.

Abstract: A display driving IC includes first channel block to Nth channel block each including M source amplifiers, N and M being an integer, source driving pads each connected to the M source amplifiers, a multiplexer configured to alternate data outputs of the source amplifiers or selectively provide a test path so that a probe test is performed on a plurality of source amplifiers for each of the first to Nth channel blocks through a test pad selected from the source driving pads, and a control unit configured to control driving of the source amplifiers and multiplexer.

Abstract: A semiconductor device includes a substrate, a first device, a second device, a ring structure, a lid structure, and a first adhesive layer. The first device is disposed on the substrate. The second device is adjacent to the first device and is disposed on the substrate. The ring structure is disposed over the substrate and the second device. The ring structure includes a cover and a leg extending out from the cover. The cover has a through opening. The lid structure is disposed over the ring structure and the first device. The lid structure includes a body and a protrusion protruding from the body. The protrusion of the lid structure is inserted into the through opening of the cover of the ring structure. The first adhesive layer is disposed between the body of the lid structure and the cover of the ring structure and includes phase change thermal interface material.

Abstract: A switched-capacitor voltage converter includes a loop regulator module, a clamp transistor, and a clamp circuit. The loop regulator module is configured to monitor electrical parameters of an input terminal and an output terminal, and output a voltage to a gate of the clamp transistor based on electrical parameters to stabilize a voltage of an output terminal of the switched-capacitor voltage converter at a target value. The clamp circuit is connected between the two terminals of the clamp transistor, such that the voltage difference between the drain and the source of the clamp transistor is less than the withstand voltage of the clamp transistor.