Patents Assigned to ON Semiconductor
  • Publication number: 20240178245
    Abstract: A photodetection that alleviates restrictions on a pixel layout in each pixel and capable of being miniaturized is provided. A photodetection device as provided includes a first substrate including a first semiconductor layer with a first surface and a second surface on a side opposite to the first surface, first and second charge accumulation sections provided on the first surface side, a first photoelectric conversion section in the first semiconductor layer, and first and second voltage application sections that apply a voltage to the first semiconductor layer between the first and second charge accumulation sections and the first photoelectric conversion section, and a second substrate including a second semiconductor layer with a third surface and a fourth surface on a side opposite to the third surface and is bonded to the first substrate, and a first pixel transistor on the third or fourth surface that outputs a pixel signal.
    Type: Application
    Filed: March 15, 2022
    Publication date: May 30, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Koichi BABA, Taiichiro WATANABE
  • Publication number: 20240178060
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Publication number: 20240179990
    Abstract: The present disclosure provides a display panel and a display device. The display panel includes a pixel group arranged in an array, where the pixel group includes: a first pixel unit, a partial region of which is provided with a first sub-pixel; a second pixel unit, a partial region of which is provided with a second sub-pixel; and a third pixel unit, a partial region of which is provided with a third sub-pixel; where the first sub-pixel, the second sub-pixel, and the third sub-pixel have different colors, and any one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is adjacent to other sub-pixels.
    Type: Application
    Filed: June 6, 2022
    Publication date: May 30, 2024
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yuan Wu, Tingting Wu
  • Publication number: 20240178005
    Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Piao CHUU, Ming-Yang LI, Lain-Jong LI
  • Publication number: 20240178015
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor device is picked up from a carrier by a pick and place device, wherein the pick and place device includes a flexible head having a bonding portion configured to be in contact with the semiconductor device, a neck portion connecting the bonding portion, wherein a minimum width of the neck portion is substantially smaller than a maximum width of the bonding portion. The semiconductor device is placed and pressed onto a substrate by the pick and place device. An encapsulating material is formed over the substrate to laterally encapsulating the semiconductor device. A redistribution structure is formed over the semiconductor device and the encapsulating material. The substrate is removed.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Wu, Hsien-Ju Tsou, Yung-Chi Lin, Tsang-Jiuh Wu
  • Publication number: 20240178058
    Abstract: A semiconductor device includes an epitaxial layer and a doped region located in the epitaxial layer. A contact structure of the semiconductor device includes: an interlayer dielectric layer, arranged on the epitaxial layer; a contact hole, including a first portion extending through the interlayer dielectric layer and a second portion extending into the doped region, where a size of the first portion is greater than a size of the second portion, the second portion is open on a bottom surface of the first portion, and a bottom surface of the second portion is arranged in the doped region; a contact layer, including a first contact layer arranged on the bottom surface of the first portion and a second contact layer arranged on the bottom surface of the second portion; and a conductive channel, arranged in the contact hole and contacting the contact layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 30, 2024
    Applicant: Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.
    Inventor: Chenhan Wang
  • Patent number: 11994777
    Abstract: The present application discloses a display panel and a display device. The display panel includes a plurality of pixel electrodes and a common electrode arranged correspondingly, and a plurality of light shielding electrodes, by opening holes on the common electrode corresponding to the light-shielding electrode or adjust a preset voltage on the light-shielding electrode, a vertical electric field is formed between the common electrode and the corresponding light-shielding electrode, which hinders a lateral movement of impurity ions and relieves a problem of line residue of currently LCD panels.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: May 28, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Baolin Chi
  • Patent number: 11994805
    Abstract: A method of operating a semiconductor apparatus includes generating an air flow that flows from a covering structure; causing a photomask to move over the covering structure such that particles attached to the photomask are blown away from the photomask by the air flow; and irradiating the photomask with light through a light transmission region of the covering structure.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Chiu-Hsiang Chen, Ru-Gun Liu
  • Patent number: 11994534
    Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Chun Chiu, Wen-Feng Liao, Hao Chen, Chun-Hsing Chen
  • Patent number: 11994558
    Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: May 28, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Han-Yun Tsai, Shih-Hung Wang, Ting-Ying Wu
  • Patent number: 11994717
    Abstract: A method includes: determining a first material and a second material of a photonic waveguide for propagating light, the photonic waveguide having a first section and a second section arranged in a first layer and a second layer, respectively, of the photonic waveguide; determining a spacing between the first layer and the second layer; determining a parameter set of a crosstalk reduction structure, according to the spacing, the first material and a wavelength of the light, to cause insertion losses of the first section and the second section to be lower than a predetermined threshold; and forming the first and second sections with the first and second materials, respectively, the first section having the crosstalk reduction structure overlapping the second section.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming Yang Chung, Chewn-Pu Jou, Stefan Rusu, Cheng-Tse Tang
  • Patent number: 11994809
    Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe positioned above the semiconductor manufacturing equipment and having a top surface and a bottom surface extending parallel to the top surface; a first branch pipe including an upstream end coupled to a source of a gas mixture and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including an upstream end and a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Patent number: 11994411
    Abstract: A vernier sensor including a coarse sensor and a fine sensor may require calibration to ensure accurate position measurements. Calibration may include determining coefficients for harmonics that can be added to the coarse sensor output and the fine sensor output to reduce harmonic distortion. The disclosure describes using the offset and variance of a difference signal as the basis for calibration. This approach is possible at least because the frequencies of the coarse sensor and fine sensor can be selected to reduce the complexity of these calculations.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 28, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jacques Jean Bertin
  • Patent number: 11995388
    Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin
  • Patent number: 11994923
    Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liu Yi, Dandan Zhu, Yuan Deng, Congyu Zhang, Neng-Hsien Lin, Tsung-Tao Wu, Fan-Hau Hsu
  • Patent number: 11994796
    Abstract: A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Jen Lai, Xin Zhou, Danping Peng
  • Patent number: 11994604
    Abstract: Techniques by a wireless to estimate the position of a remote device are disclosed. A main receiver of the wireless device may determine multiple first phase values of the RF signal received through a first antenna during multiple time intervals. An auxiliary receiver may determine multiple second phase values of the RF signal received through an array of auxiliary antennas during the multiple time intervals. Each of the second phase value may correspond to the RF signal received through one antenna of the array during one of the time interval. The wireless device may determine an oscillator offset between a local oscillator of the main transceiver and a local oscillator of the auxiliary receiver. The wireless device may estimate an angle of arrival (AoA) of the RF signal or a distance based on the multiple first phase values and the multiple second values by compensating for the oscillator phase offset.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 28, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pouria Zand, Kiran Uln, Victor Simileysky
  • Patent number: 11994961
    Abstract: An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 28, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Wei Yu, Chun-Hsing Hsieh
  • Patent number: 11993293
    Abstract: Evacuation control such as deceleration or stop of a vehicle is executed in response to an application from a driver of the vehicle for refusal of switching to manual driving.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 28, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Eiji Oba
  • Patent number: 11993854
    Abstract: In an etch process chamber, oscillators are positioned a predetermined distance away from an outer wall and coupled to a microwave generator. An inner wall of the process chamber on which particulates such as polymers adhere from the etch process is vibrated via operations of the oscillators. A gas flows into the cavity defined by the inner wall to collect the displaced particulates, which is then pumped out of the cavity to clean the process chamber. A controller identifies the polymer recipe used during the etch process and selects an oscillation program from memory. A microwave generator, controlled by the controller, is directed to generate microwaves at preselected frequencies determined from the program. The microwave frequencies are communicated to the oscillators, which then vibrate the inner wall at such received frequencies.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsun Tseng, Yan-Hong Liu