Abstract: A semiconductor device includes a high electron mobility transistor (HEMT) disposed in an annular active element region, and a resistor disposed in a passive element region surrounded by the annular active element region. The HEM includes a first portion of a compound semiconductor barrier layer stacked on a first portion of a compound semiconductor channel layer. A source electrode, a gate electrode, and a drain electrode are disposed on the first portion of the compound semiconductor barrier layer. The resistor includes a second portion of the compound semiconductor barrier layer stacked on a second portion of the compound semiconductor channel layer. An input terminal electrode is disposed on the second portion of the compound semiconductor barrier layer and located at the center of the passive element region.

Abstract: Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: A system for controlling charging of a battery, the system comprising: charging circuitry for supplying a charging current or voltage to the battery, wherein the charging circuitry is configured to periodically detect an impedance of the battery and to control the charging current or voltage based on the detected impedance.

Abstract: A circuit for preventing current backflow includes: a signal connection terminal, a power input terminal, an internal power supply terminal, an electrostatic protection circuit, a first switch element and a cut-off control circuit. The electrostatic protection circuit is coupled to the signal connection terminal and the internal power supply terminal. The first switch element is coupled between the power input terminal and the internal power supply terminal. The cut-off control circuit is coupled to the signal connection terminal, the power input terminal and the first switch element. The cut-off control circuit controls the switching of the first switch element according to a voltage of the signal connection terminal and a voltage of the power input terminal.

Abstract: A method includes the following steps. A substrate is etched, forming a core structure protruding out of a plane of the substrate. Shallow trench isolation (STI) features are formed on opposite sides of the core structure. The substrate and a lower portion of the core structure are doped to form a first source/drain region with a first doping concentration. A barrier layer is grown on an upper portion of the core structure. A first spacer is formed covering the STI features and covering the lower portion of core structure. A shell is formed wrapping the upper portion of the core structure and the barrier layer. The shell and the upper portion of the core structure have different doping conductivity types. A second source/drain region is formed with a second doping concentration over the shell. The first doping concentration and the second doping concentration are different from each other.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a channel layer, a barrier layer and a P-type semiconductor layer sequentially stacked in a first direction. The P-type semiconductor layer includes a high-resistance passivation region and an activation region, and the high-resistance passivation region is located on a side, away from the substrate, of the activation region. When a semiconductor device is in an off state, the activation region of the P-type semiconductor layer may deplete 2DEG at the channel to realize an enhancement-mode device. The high-resistance passivation region is passivated to form a high-resistance structure, which may reduce a gate leakage current in the off state and improve power characteristics of the semiconductor device.

Abstract: An image sensor may include an array of pixels and associated delay calibration circuitry for determining an amount of delay for row control signals. The delay calibration circuitry can include circuitry for generating a calibration row control signal, circuitry for propagating the calibration row control signal down a row of dummy pixels, and one or more sampling circuits coupled to one or more tap points in the row of dummy pixels for monitoring when the calibration row control signal arrives at the one or more tap points. The array of pixels can output signals during normal operation. The image sensor may include column readout circuitry for reading out the signals from the array of pixels. The column readout circuitry can be controlled using sampling signals that are progressively delayed based on count values output from the one or more sampling circuits.

Abstract: A semiconductor device includes an active region; a substrate; an epitaxial structure; an electrode structure, and the electrode structure including a plurality of ohmic contact electrodes; a first dielectric layer; an electrode connection line, the electrode connection line including an ohmic contact electrode connection line, and the ohmic contact electrode connection line being electrically connected to the ohmic contact electrode; an second dielectric layer; an electrode bonding pad, the electrode bonding pad including an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line, and at least a part of the ohmic contact electrode bonding pad being located in the active region, reducing a parasitic capacitance between the ohmic contact electrode bonding pad and the substrate, and further satisfying high requirements on an input capacitance and an output capacitance of the semiconductor device.

Abstract: A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

Abstract: A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer formed on the substrate, a well region extending from a top surface of the epitaxial layer into the epitaxial layer, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductivity type, the well region has the second conductivity type, and the drift region has the first conductivity type. The gate structure that extends from the top surface of the epitaxial layer penetrates the well region and is in contact with the drift region. The conductive structure is formed in the drift region and disposed below the gate structure. A gate electrode of the gate structure is separated from the underlying conductive structure by the gate dielectric layer of the gate structure.

Abstract: The present disclosure provides a luminance adjustment method and device of a display panel. In the method, firstly, a difference between the luminance parameters of different regions of the target panel are obtained, and temperatures of different regions of the target panel are obtained according to the difference of the luminance parameters of the different regions of the target panel. Then, luminance compensation parameters of the corresponding regions are obtained according to a correlation of the luminance to the temperature and a difference of the operating temperatures of the different regions, and finally, the luminance of a corresponding region is compensated according to the luminance compensation parameters.

Abstract: A semiconductor device, which comprises a semiconductor substrate, an epitaxial layer, first metal structures, first doped regions, second metal structures, second doped regions, a conductive layer and a Schottky layer. The epitaxial layer is disposed on the semiconductor substrate. The first metal structures are disposed in the epitaxial layer. The first metal structures extend along a first direction and have a first width in a second direction. The first doped regions are disposed in the epitaxial layer and extend from below each first metal structure to the sidewall of each first metal structure. The second metal structure is disposed in the epitaxial layer. The second metal structures extend along the first direction and have a second width in the second direction, wherein the first width is larger than the second width. The conductive layer is disposed under the semiconductor substrate, and the Schottky layer is disposed on the epitaxial layer.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: Provided is a semiconductor device including a stack including a semiconductor substrate, an opening provided extending from a first surface of the stack and filled with an insulating material, a pad electrode provided at a bottom of the opening, a wiring layer provided in a planar region of the stack overlapping a planar region where the opening is provided in plan view from the first surface, the wiring layer being electrically being connected to the pad electrode, and a through electrode provided in a planar region different from the planar region where the opening is provided in the plan view and provided extending from a second surface of the stack opposite to the first surface.

Abstract: A method for forming a FinFET device structure is provided. The FinFET device structure includes a first fin structure extending above a substrate, and a first liner layer formed on a first sidewall surface of the first fin structure. The FinFET device structure includes a gate dielectric layer formed over the first fin structure and the first liner layer, wherein a sidewall surface of the gate dielectric layer is aligned with a sidewall surface of the first liner layer.

Abstract: Disclosed are a package, a package structure and a method of manufacturing a package structure. In one embodiment, the package includes a die, a plurality of through vias, at least one dummy structure, an encapsulant and a redistribution structure. The plurality of through vias surround the die. The at least one dummy structure is disposed between the die and the plurality of through vias and adjacent to at least one corner of the die. The encapsulant encapsulates the die, the plurality of through vias and the at least one dummy structure. The redistribution structure is disposed on the die, the plurality of through vias, the at least one dummy structure and the encapsulant and electrically connected to the die and the plurality of through vias.