Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: In an aspect, an electronic device can include a substrate, a semiconductor layer overlying the substrate and including a mesa adjacent to a trench, and a doped region within the semiconductor layer. The doped region extends across an entire width of the mesa and contacts the lowermost point of the trench. A charge pocket can be located between an elevation of the peak concentration of the doped region and an elevation of the upper surface of the substrate. In another aspect, a process includes patterning a semiconductor layer to define a trench, forming a sacrificial layer within the trench, removing the sacrificial layer from a bottom of the trench, doping a portion of the semiconductor layer that is along the bottom of the trench while a remaining portion of the sacrificial layer is along a sidewall of the trench.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: A method of forming a semiconductor device includes the following steps. A 2D material layer is formed over a bottom metal layer. A top metal layer is formed over the 2D material layer. An oxidation treatment is performed to the 2D material layer to form an oxide region interfacing both the 2D material layer and the top metal layer.

Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Abstract: A current sensing system for sensing current through first and second circuit elements of a circuit in which the first and second circuit elements are active in respective first and second phases of an operational cycle of the circuit, the current sensing system comprising: first current sensing circuitry for sensing a current through the first circuit element; second current sensing circuitry for sensing a current through the second circuit element; and summation circuitry coupled to an output of the first current sensing circuitry and an output of the second current sensing circuitry, wherein the summation circuitry is configured to output a summation signal indicative of a sum of the sensed current through the first circuit element and the sensed current through the second circuit element so as to provide an indication of a total current drawn over an operational cycle of the circuit.

Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.

Abstract: In an embodiment of the techniques presented herein, a charging system includes an input port, a wireless charging unit, having a magnetic charging interface, and a wireless charging controller configured to generate a magnetic charging signal at the magnetic charging interface based on a first connection state of the magnetic charging interface, and a universal serial bus power delivery (USB-PD) power adaptor, having an output port, and a USB-PD controller configured to deliver power to the output port, wherein a first portion of available power at the input port is allocated to the wireless charging unit for generating the magnetic charging signal responsive to the first connection state indicating a connected device, and a second portion of the available power at the input port is allocated to the USB-PD adaptor based on the first portion allocated to the wireless charging unit.

Abstract: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. In addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. The method includes forming a backside conductive contact in the contact opening.

Abstract: A method includes irradiating debris deposited in an extreme ultraviolet (EUV) lithography system with laser, controlling one or more of a wavelength of the laser or power of the laser to selectively vaporize the debris and limit damage to the EUV) lithography system, and removing the vaporized debris.

Abstract: A MEMS package includes an interconnect structure disposed on a wafer. A first device substrate including a first MEMS device and a second device substrate including a second MEMS device are laterally separated from each other, disposed on the wafer and bonded to the interconnect structure. A first cap substrate with a first cavity is bonded to the first device substrate. A second cap substrate with a second cavity is bonded to the second device substrate. A getter is disposed on the interconnect structure and directly under the second MEMS device. The first cavity has a first pressure, and the second cavity has a second pressure lower than the first pressure.

Abstract: A transformer is disclosed. The transformer includes a magnetic core having a central region, a primary winding extending around the central region, a first secondary winding including a first conductor having one or more first turns extending around the central region, where the first conductor has a first width and is arranged to receive electromagnetic flux from the primary winding, and a second secondary winding including a second conductor having one or more second turns extending around the central region, where the second conductor has a second width and is arranged to receive electromagnetic flux from the primary winding. In one aspect, a number of the one or more second turns is greater than a number of the one or more first turns and the first width is greater than the second width.

Abstract: An inductive position sensor can include a first target coil, included in a target, and including a first outer lobe that has a size based on a first shift ratio of a harmonic period of a receiver coil, and a first inner lobe having a size based on a second shift ratio of the harmonic period where the harmonic period corresponds with a harmonic and the first shift ratio is different from the second shift ratio. The inductive position sensor also include a second target coil including a second outer lobe having a size based on the second shift ratio, and a second inner lobe having a size based on the first shift ratio.

Abstract: A long-lifetime light-emitting device is provided. The light-emitting apparatus includes a first light-emitting device and a first color conversion layer. The first color conversion layer contains a first substance. An EL layer of the first light-emitting device includes a first layer, a second layer, a third layer, a light-emitting layer, and a fourth layer in this order from the anode side. The first layer contains a first organic compound and a second organic compound. The second layer contains a third organic compound. The third layer contains a fourth organic compound. The light-emitting layer contains a fifth organic compound and a sixth organic compound. The fourth layer contains a seventh organic compound. The first organic compound is an organic compound having an electron accepting property to the second organic compound. The fifth organic compound is an emission center substance. The HOMO level of the second organic compound is higher than or equal to ?5.7 eV and lower than or equal to ?5.4 eV.

Abstract: A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to continuously operate the first buck converter, sense a voltage at the junction, compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage disables the second buck converter. In yet another aspect, the control circuit is arranged to continuously operate the first buck converter, compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

Abstract: Electronic paper display devices and manufacturing methods thereof are provided. The electronic paper display device includes an upper substrate, a lower substrate, and an electrophoretic display layer. A side of the upper substrate is provided with a first electrode layer thereon. A side of the lower substrate facing the first electrode layer is provided with a second electrode layer thereon. The first electrode layer and the second electrode layer are arranged opposite to each other at a preset interval. The electrophoretic display layer is disposed between the first electrode layer and the second electrode layer, and includes a color resistance layer and a black matrix. The black matrix has openings, the color resistance layer includes a plurality of color resistance blocks arranged corresponding to the openings. Each color resistance block is provided with a micro-cavity, and the micro-cavity is filled with electronic ink containing black and white particles.