Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.

Abstract: A solid-state imaging element of an embodiment of the present disclosure includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel transistor provided on one surface of the semiconductor substrate; and an element separation section provided in the semiconductor substrate and including a first element separation section and a second element separation section that have mutually different configurations, the element separation section defining an active region of the pixel transistor, in which the second element separation section has, on a side surface, a first semiconductor region and a second semiconductor region that have mutually different impurity concentrations in a depth direction of the second element separation section.

Abstract: Provided is an imaging device capable of suppressing an influence of flare. An imaging device according to the present disclosure includes: a pixel region in which a plurality of pixels that performs photoelectric conversion is arranged; an on-chip lens provided on the pixel region; a protective member provided on the on-chip lens; and a resin layer that adheres between the on-chip lens and the protective member, in which when a thickness of the resin layer and the protective member is T, a length of a diagonal line of the pixel region viewed from an incident direction of light is L, and a critical angle of the protective member is ?c, T?L/2/tan?c (Formula 2) or T?L/4/tan?c (Formula 3) is satisfied.

Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a gate dielectric layer disposed over the fin structure. The semiconductor device includes an interfacial layer over a top portion of the gate dielectric layer. A bottom portion of gate dielectric layer is free of contact with the interfacial layer. The semiconductor device includes a gate structure straddling the fin structure.

Abstract: An imaging element according to the present disclosure includes a pixel, an overflow path, a pixel isolation unit, a pixel isolation electrode, an in-pixel isolation unit, and an in-pixel isolation electrode. The pixel includes a plurality of photoelectric conversion units formed in a semiconductor substrate having an interconnect region arranged on a front surface side and performs photoelectric conversion of incident light. The overflow path mutually transfers charges between the plurality of photoelectric conversion units. The pixel isolation unit is at a boundary of the pixel. The pixel isolation electrode is in the pixel isolation unit, and a first bias voltage is applied to the pixel isolation electrode. The in-pixel isolation unit isolates the plurality of photoelectric conversion units from each other. The in-pixel isolation electrode is arranged in the in-pixel isolation unit, and a second bias voltage is applied to the in-pixel isolation electrode.

Abstract: Embodiments of the present disclosure are directed to a square wave chamfering circuit and a display panel. A control circuit controls the output node to output a chamfering signal based on a current through a path between the control circuit and the second power supply end. By using the control circuit to control an output node to output a chamfering signal based on a current through the control circuit and the second power supply end, a slow decline slope of the voltage output by the output node solves the problem of the large voltage drop of the display panel driving voltage.

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

Abstract: Disclosed are a composite substrate, an epitaxial wafer, and a semiconductor device. The composite substrate includes: a support substrate layer; a first alumina layer disposed on the support substrate layer; and a sapphire substrate layer disposed on the first alumina layer. The first alumina layer may increase a bonding force between the sapphire substrate layer and the support substrate layer and release a stress between the sapphire substrate layer and the support substrate layer. Meanwhile, the existence of the first alumina layer may improve a breakdown voltage of a material without increasing a thickness of the sapphire substrate layer.

Abstract: A special-shaped thin-film transistor and an array substrate are provided. The special-shaped thin-film transistor includes a first gate portion, a first compensation electrode, and a first source electrode. The first compensation electrode is connected to the first gate portion. The first source electrode includes a first extension part, a first source portion, and a second extension part which are connected in sequence. Part of the first extension part overlaps the first gate portion, and part of the second extension part overlaps the first compensation electrode.

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Abstract: A switched-capacitor voltage converter including a switched-capacitor voltage conversion circuit, a loop regulator circuit, a first clamp transistor, a second clamp transistor, a first clamp circuit, and a second clamp circuit is provided. The loop regulator circuit is configured to monitor electrical parameters of any one or both of an input terminal and an output terminal of the switched-capacitor voltage converter, and output a voltage to a gate of the first clamp transistor or the second clamp transistor according to one or more electrical parameters to stabilize the one or more electrical parameters at their corresponding target values. According to the present disclosure, the loop regulator circuit is additionally configured in the switched-capacitor voltage converter, and two back-to-back clamp transistors are disposed between the input terminal and a reference terminal of the switched-capacitor voltage converter.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Abstract: A display panel and an electronic device are provided. The display panel includes a first stacked layer and a second stacked layer disposed on a base substrate. Openings are defined on the second stacked layer corresponding to transparent areas, and the openings penetrate the second stacked layer, the first stacked layer, and at least part of the base substrate. The first stacked layer in the transparent areas is removed by forming the openings in the transparent areas. Therefore, transmittance in the transparent areas is improved, thereby solving a problem of poor transmittance in current transparent display screens.

Abstract: A system may include a pulse-width modulation mode path configured to drive a load at an output of the system in a first mode of operation, a linear mode path configured to drive the load in a second mode of operation, a common mode control feedback loop configured to set a value of a common mode output signal at the output in the second mode of operation, and an auxiliary circuit coupled to the common mode feedback control loop and configured to maintain a state of the common mode feedback control loop during the first mode of operation as the state was or will be during the second mode of operation.

Abstract: A thin film transistor and an array substrate, including a light-shielding layer and an active layer. The light-shielding layer includes a first light-shielding pattern, a second light-shielding pattern and a third light-shielding pattern. The active layer includes a channel area, a first conductive area and a second conductive area located on both sides of the channel area. An orthogonal projection of the first light-shielding pattern on the substrate at least covers an orthogonal projection of the channel area on the substrate. An orthographic projection of the second light-shielding pattern on the substrate overlaps at least a part of an orthographic projection of the first conductive area on the substrate. An orthographic projection of the third light-shielding pattern on the substrate overlaps at least a part of an orthographic projection of the second conductive area on the substrate.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: The present application provides a display panel and a display terminal. The display panel includes a display area and a fan-out area. The fan-out area includes a plurality of fan-out wirings, and each of the fan-out wirings includes a straight section and an inclined section. The display panel further includes a plurality protection members arranged in one-to-one correspondence with the inclined sections of the plurality of fan-out routing lines, and each of the protection members is disposed close to a corresponding one of the inclined sections.

Abstract: The present invention relates to the field of chip packaging technology, and proposes a package structure and method of sensing chip. The package structure comprising: a substrate; a silicon interposer; and a plurality of chips, the plurality of chips comprising sensing chips as well as non-sensing chips, wherein the non-sensing chips are molded with molding compound and the sensing chips are exposed. By arranging a protective cover above the sensing chip before the front side of the chip is molded, and grinding off the top of the protective cover after molding, the present invention can well solve the problem that the sensing signal of the sensing chip cannot penetrate the molding compound in the prior art, and can be effectively used for the packaging of the sensing chip.

Abstract: Embodiments of the present disclosure disclose a display panel, a display device, and a method for manufacturing the display panel. The display panel includes an array substrate, an anode layer, a pixel definition layer, a fence layer, and a cathode layer. The array substrate includes an lap layer, and the lap layer includes a lap portion. A first opening on the anode layer exposes the lap portion. The fence layer includes a fence portion, and the fence layer includes a fence portion extending along an edge of the second opening. In the present disclosure, lap effect between the cathode layer and the lap portion can be improved by setting the fence portion.

Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; forming a first redistribution structure on the carrier, the first redistribution structure including a first area and a second area; forming a conductive pillar on the first redistribution structure in the first area, the conductive pillar being electrically connected to the first redistribution structure; providing a device chip, including a first side and a second side opposite to the first side; bonding the second side of the device chip to the first redistribution structure in the second area, the device chip being electrically connected to the first redistribution structure; providing a substrate including a bonding surface; and bonding the first side of the device chip and the conductive pillar to the bonding surface, the device chip being electrically connected to the substrate, and the conductive pillar being electrically connected to the substrate.