Abstract: A virtual data storage system stores data as data objects to a plurality of storage devices in accordance with storage management policies. Storage pools define groups of medial that are to be treated in a uniform manner. A policy is composed of a series of policy copy/delete rules that direct movement of data objects into the storage pools. Copy and delete actions are preformed to manage copies of data objects among the storage pools in accordance with the policy. As an extension of the storage management policies, the process of creating export media sets is automated. These processes can also be used to create backup media. When an export media set is created, subsequent commands are prevented from modifying the media in the export media set. When a backup is created, subsequent commands are prevented from overwriting media containing data referred to by the manifest media for the backup.

Abstract: Embodiments of a system that determines a condition associated with an integrated circuit disposed on a circuit board are described. During operation, the system receives electromagnetic-interference (EMI) signals from one or more antennas while the integrated circuit is operating, where the one or more antennas are disposed on the circuit board. Then, the system analyzes the received EMI signals to determine the condition.

Abstract: A method, and corresponding system, is provided for generating replicas or copies of data objects that are used to serve data streams. The method includes determining one of the storage devices is operating at a load above a predetermined overload value. The method continues with identifying the data objects being served by data streams from the near overload storage device and then, selecting one of these served data objects for replication. To create a replica, the method includes writing data from the selected data object to another less busy one of the data storage devices, with the writing being done using data from one or more of the streams being served from the selected data object on the near-overload storage device. During replica creation, one or more streams from the selected data object provide data concurrently to a stream consumer or client device and to the replica.

Abstract: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency.

Abstract: A data deduplication method providing direct look up and storage in an instance repository (IR). The method includes receiving a data object and processing the data object to generate a fingerprint that includes a location component, which defines a file location within the IR such as by first using a hash function to create a hash for the data object and parsing the hash value into sub-strings defining sub-directories of the IR. The method includes determining whether the data object is a duplicate by verifying the presence of a file in the IR at the file location. Determining if the data is unique involves performing a system call on the IR providing the location component as the file path. The method includes, when a file is not in the IR, updating the IR to store the data object as a file at the file location defined by the location component.

Abstract: In general, the invention relates to a method for processing packets. The method includes receiving a first packet by a network interface card (NIC) connected to a host, classifying the first packet using a classifier, sending the first packet to a receive ring based on a classification of the first packet by the classifier, and sending the first packet from the receive ring to a first virtual network interface card (VNIC) located on the host. The method further includes determining, using a first policy associated with the first VNIC, whether to process the first packet using offload hardware. When the first packet is to be processed using the offload hardware, the method includes sending the first packet to the offload hardware, receiving a first processed packet from the offload hardware by the first VNIC and sending the first processed packet from the first VNIC to a first packet destination.

Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

Abstract: A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.

Abstract: A method, apparatus and computer program product for providing Global Account Lockout (GAL) using an Ordered Messaging Service (OMS) is presented. A database operation is received from a client, and a determination made regarding whether the operation contains an authentication mechanism. When the operation does not contain an authentication mechanism, then the operation is returned from. When the operation does contain an authentication mechanism, then the following steps are performed: locating the entry and checking its authentication mechanism, determining whether the authentication mechanism in the operation is good, sending a bind message to a GAL manager, checking and updating GAL state, committing updates to GAL state, and returning operation to the client.

Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Abstract: A method including receiving a set of input data in a first matrix format. The method further includes compressing the set of input data to obtain a first set of compressed data in a second matrix format, where compressing the set of input data includes using a quantization equation, the quantization equation including Yq(i,j)=[(Y(i,j)+offset)<<n]/qs, where Yq(i,j) represents a coefficient in a matrix of the first set of compressed data having a coordinate (i,j), Y(i,j) represents a coefficient in a matrix of the set of input data having the coordinate (i,j), offset is an integer, << is a first bit-wise shift operator, n is an integer, qs is a real number. The method also includes sending the first set of compressed data to a first destination.

Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.

Abstract: A network, including: a first tile having a processor, a first top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the first top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, the intermediate, and the second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, the second bottom brick, and the third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.

Abstract: Provided is a method and system for controlling access to a mail transfer agent (MTA), included in a mail server infrastructure (MSI), by a client, which is either a mail user agent (MUA) or an MTA not included in the MSI, and features determining whether to grant access to a client based upon the accesses made to this and other MTAs at the present time or in the past. To that end, the method includes receiving a request for access to the one of the plurality of mail transfer agents by the client. Access between the client and other MTAs is determined to obtain an existing access profile. A conditional access profile is developed from the existing access profile and from the request. The conditional access profile is compared against a permissible access profile to determine whether to grant the request. If it is determined that the conditional access profile does not violate the rules and criteria, the access is granted. Otherwise, access is denied.

Abstract: The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a single SIMD pipeline capable processor. This transformation permits the use of Fletcher/Alder checksums on processors where the performance of SIMD instructions are sub-optimal, on CMT processors that support a single SIMD pipeline as well as other processors that can be configured by executing software to implement SIMD operations for a single SIMD pipeline. The implementation of the process with this transformation on a general-purpose computer system transforms that general-purpose computer system into a special-purpose computer system that uses a single SIMD pipeline to generate a Fletcher/Alder checksum. The elimination of integer multiplications in the generation of the partial checksums results in a significant improvement in performance.

Abstract: A video encoder/adapter comprises a virtual display module for partial rendering of a software application image. The virtual display module presents to the software application a virtual display device upon which the software application window is displayed. From the virtual display device, the user identifies one or more portions of the virtual software application window that are to be rendered on the actual display device.

Abstract: A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.

Abstract: A method for arithmetic expression optimization comprises validating at least one input stack associated with a first instruction operable on at least one operand of a first type and optimizing the first instruction to a second instruction operable on at least one operand of a second type that is smaller than the first type based at least in part on the relative size of the first type and the second type. The method also comprises matching the second type with an operand type of at least one operand in the at least one input stack associated with the second instruction. The matching comprises changing the type of instructions in a chain of instructions to equal the second type if the operand type is less than the second type. The chain is bounded by the second instruction and a third instruction that is the source of the at least one operand.

Abstract: A method for executing an application on multiple nodes includes synchronizing a first clock of a first node and a second clock of a second node, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, and configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain. Configuring the hypervisor includes allocating a first number of cycles of the first clock to the first privileged domain. Configuring the second hypervisor includes allocating the first number of cycles of the first clock to the second privileged domain. The method further includes executing the application in the first application domain and the second application domain. The first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Abstract: A method for implementing a just-in-time compiler involves obtaining high-level code templates in a high-level programming language, where the high-level programming language is designed for compilation to an intermediate language capable of execution by a virtual machine, and where each high-level code template represents an instruction in the intermediate language. The method further involves compiling the high-level code templates to native code to obtain optimized native code templates, where compiling the high-level code templates is performed, prior to runtime, using an optimizing static compiler designed for runtime use with the virtual machine. The method further involves implementing the just-in-time compiler using the optimized native code templates, where the just-in-time compiler is configured to substitute an optimized native code template when a corresponding instruction in the intermediate language is encountered at runtime.