Abstract: A method for executing a job using a remote file system that includes obtaining a plurality of job data files by the remote file system, wherein the plurality of job data files are created on the remote file system, detecting a job request for the job in an input directory to obtain a detected job request, wherein the job request is generated by a client, and executing the job based on the job data files and the detected job request, wherein executing the job generates an output file, wherein the remote file system is accessible using a local file system of the client.

Abstract: In one embodiment, an apparatus for directory-based web service distribution is disclosed. The apparatus includes a directory and a request client to initiate a request for a web service, the request client including an application middleware having invocation framework with embedded distribution logic to distribute the request to a destination pod, the destination pod to compute a subset of a state associated with the web service, wherein the distribution logic to distribute the request based on a lookup value extracted from the request and submitted to the directory to determine the destination pod. Other embodiments are also disclosed.

Abstract: A hybrid integrated module includes a semiconductor die mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical waveguide that conveys an optical signal, which is fabricated on a silicon-on-insulator (SOI) wafer in which the back-side silicon substrate or handler has been completely removed. Moreover, an optical device may be disposed on the bottom surface of an oxide layer (such as a buried-oxide layer) in the integrated device, and the geometry and materials in the integrated device may be selected and/or defined so that the optical signal is evanescently coupled between the optical waveguide and the optical device.

Abstract: Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.

Abstract: A method for auditing and correcting at least one component in a system, involving defining a first audit rule for the at least one component, wherein the first audit rule defines a check to be performed on the at least one component, defining a corrective action associated with the first audit rule, executing the first audit rule for the at least one component and the corrective action associated with the first audit rule, wherein the first audit rule and the corrective action are executed to identify and remove a problem in the system, and performing a system action upon successful execution of the corrective action.

Abstract: Leaked memory in a computer system is detected and recovered by first detecting memory leakage within the computer system based on nonlinear and non-parametric time-series regression analysis of software telemetry data generated by one or more software process running on the computer system. If existence of memory leakage is detected, then memory that has leaked is specifically identified and recovered. This is done by halting one or more of the software processes, generating a core image file or files of the halted software process(es), and re-starting the halted process or processes without waiting for analysis of the core image file(s). Then, the core image file is evaluated to specifically identify leaked memory in the computer system based on the core image file. Finally, the identified leaked memory is recovered.

Abstract: A heat sink for use with a heat generating component includes a molded cooling block including a molded cooling passage for receiving a cooling medium. The cooling block is configured to be positioned in sufficient heat transfer relationship with respect to the heat generating component so that the cooling medium receives heat from the heat generating component.

Abstract: A method of filling dcaps in an integrated circuit includes identifying a set of dcap-eligible areas of the integrated circuit for areas large enough to accommodate at least one dcap cell having a selected size smaller than a default size. The dcap cell includes at least one built-in power track. A set of dcap cells are filled in the identified set of dcap-eligible areas. Each of the built-in power tracks included in the set of dcap cells is connected to a corresponding power grid. An integrated circuit including a power grid channel formed between at least two power grids and a plurality of dcaps including a first dcap included in a dcap cell, the dcap cell including built-in power tracks, each one of the built-in power tracks being connected to a corresponding one of the at least two power grids is also described.

Abstract: Functionality from an object file can be incorporated into an already existing binary file. Functions from the object file can be intelligently inserted into the binary file with the guidance of control flow analysis of both the binary file and the object file. Symbols not defined in the symbol table of the binary file are added to the symbol table of the binary file. When symbols of the object file and the binary file overlap, then priority is given to the object file symbol definitions. The ability to incorporate functionality from an object file into an existing binary file reduces logistical overhead and provides flexibility in code development and maintenance.

Abstract: A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without using the device controller hardware/firmware so fencing can be provided with storage devices that do not support disk reservation operations, such as with non-SCSI compliant disks. A polling thread on each node periodically reads a designated storage space on the shared storage device at a polling interval to determine if its corresponding node registration key is present, and halts the node if the key has been removed. A cluster membership agent removes a corresponding node registration key from the designated storage space of the shared storage device and publishes new membership information indicating that the corresponding node has departed the cluster only after delaying for a time period greater than the polling interval.

Abstract: A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for servers processing input data regardless of whether the input data is located in an attachment to a message from a client. The server receives a message from the client instructing the server to process data. Then, the server determines whether the data is located in an attachment to the message, and if the data is located in the attachment, moves the data to another location other than in the attachment.

Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

Abstract: A mechanism for enabling nodes on a network to collaboratively exchange sets of rendering information respecting a file. Each node maintains its own copy of the file, and each node may access its copy of the file. Whenever a node does access the locations of the file, that node sends out a rendering information message. The rendering information message comprises the set of rendering information for the file that has been updated. The rendering information message is forwarded to each of the other nodes. When each of the other nodes receives the rendering information message, it stores the set of rendering information contained therein to a rendering history associated with a user. In this manner, histories of access in the file by all users are exchanged among the nodes, and the user on each node is able to see rendering information generated by users on the other nodes.

Abstract: Techniques for controlling a thread on a computerized system having multiple processors involve accessing state information of a blocked thread, and maintaining the state information of the blocked thread at current values when the state information indicates that less than a predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such techniques further involve setting the state information of the blocked thread to identify affinity for a particular processor of the multiple processors when the state information indicates that at least the predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such operation enables the system to place a cold blocked thread which shares data with another thread on the same processor of that other thread so that, when the blocked thread awakens and runs, that thread is closer to the shared data.

Abstract: A method for processing packets. The method includes receiving a first packet by a network interface card (NIC) from a network, determining, using a first classification level, a first receive ring group (RRG) for the first packet, determining, using a second level classification, a first receive ring (RR) in the first RRG for the first packet, sending the first packet to the first RR, and sending the first packet from the first RR to a host operatively connected to the network interface card, wherein the first packet is received by a first virtual network interface card (VNIC) associated with the first RRG, where the first RRG is located in the NIC.

Abstract: A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register, a low threshold register, and a high threshold register. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action.

Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.

Abstract: Transactional Lock Elision (TLE) may allow threads in a multi-threaded system to concurrently execute critical sections as speculative transactions. Such speculative transactions may abort due to contention among threads. Systems and methods for managing contention among threads may increase overall performance by considering both local and global execution data in reducing, resolving, and/or mitigating such contention. Global data may include aggregated and/or derived data representing thread-local data of remote thread(s), including transactional abort history, abort causal history, resource consumption history, performance history, synchronization history, and/or transactional delay history. Local and/or global data may be used in determining the mode by which critical sections are executed, including TLE and mutual exclusion, and/or to inform concurrency throttling mechanisms. Local and/or global data may also be used in determining concurrency throttling parameters (e.g.

Abstract: A computer readable medium including instructions executable by a processor to perform a method, the method including obtaining a packet by a load balancer, obtaining queued packet information for a plurality of target hosts operatively connected to the load balancer, selecting the one of the plurality of target hosts using the queued packet information, and sending the packet to the selected target host using a first communication channel between the load balancer and the selected target host.