Abstract: A method for discovering managed systems in a network including classifying a first managed system associated with a first active Internet Protocol (IP) address in the network using a plurality of network protocols, identifying a set of drivers using the classification, where the set of drivers are configured to obtain first management information about the managed system, obtaining a first set of drivers, populating a data model with the first management information obtain using at least one of the first set of drivers, and managing the first managed system using the data model.

Abstract: An integrated circuit that includes an optical waveguide defined in a semiconductor layer is described. In this integrated circuit, light is coupled between the optical waveguide and an optical modulator, which is disposed on the optical waveguide, using 3-dimensional (3-D) taper structures that are proximate to the ends of the optical modulator. The cross-sectional areas of these 3-D taper structures transition, over a distance, from that of the optical waveguide (distal from the optical modulator) to that of optical modulator (proximate to the ends of the optical modulator). In this way, a spatial extent of an optical mode in the optical waveguide and a spatial extent of the optical mode in the optical modulator may be approximately matched to reduce the optical loss when the light is coupled to or from the optical modulator.

Abstract: A system provides a registration client capable of querying a network to discover at least one asset existing on the network. The system receives, at the registration client, registration information from at least one asset. The registration client receives the registration information as a result of an interrogation of at least one asset. The system registers at least one asset using the registration information received from at least one asset. The registration client registers the asset.

Abstract: Described is a system that tracks enregistered memory locations. The system receives program object code that enregisters a memory location (e.g., a set of data at a given memory address) and executes the program code using a thread. Enregistering memory locations involves using additional registers to cache frequently used memory locations while the object code is executing, these additional registers being available on an architecture on which the program executes, but generally not available on an architecture for which the object code was generated. After enregistering the memory location, the system uses a table that identifies enregistered memory locations to track the associated memory address and a thread identifier for the thread. The system checks this table during memory accesses to ensure that other threads attempting to access an enregistered memory location receive a current value for the enregistered memory location.

Abstract: A method and system for increasing programmability and scalability of a multi-processor network. A system includes two or more nodes coupled via a network with each node comprising a processor unit and memory. The processor unit includes one or more processors and a wiretap unit. The wiretap unit is configured to monitor memory accesses of the processors. A transaction may execute a number of read and/or write operations to memory. The nodes are configured to replicate one or more portions of memory; detect data conflicts to memory; and restore memory to pre-transaction state if needed.

Abstract: The invention provides a networking system, network system gateway, and method for managing the transfer of data between networks interconnected through the gateway. The gateway manages the communication paths and commands used in transferring data, as well as the logins associated with each network. The gateway further provides the ability to buffer data in order to accommodate latencies within the networks. Additionally, the gateway provides the ability to pipeline data across the networks.

Abstract: A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.

Abstract: A statistical system and method for generating patterns and performing online handwriting recognition based on those patterns. A plurality of predetermined patterns may be generated by performing feature extraction operations on one or more character samples utilizing a Gabor filter. An online handwritten character may be acquired. The online handwritten character may be pre-processed. One or more feature extraction operations, utilizing a Gabor filter, may be performed on the online handwritten character to produce a feature vector. One or more patterns may be generated, using a statistical algorithm, for the online handwritten character, based on the feature vector. The online handwritten character may be statistically classified based on a comparison between the one or more patterns generated for the online handwritten character and the plurality of predetermined patterns.

Abstract: A method for processing a packet that includes receiving a packet for a target, classifying the packet, and sending the packet to a receive ring based on the classification. The method also includes obtaining an identifier (ID) associated with the target based on the classification, and sending a request for virtual memory that includes the ID. Furthermore, the method includes determining, using the ID, whether the target has exceeded a virtual memory allocation associated with the target. In addition, the method includes allocating the virtual memory, storing the packet in the virtual memory, and updating the virtual memory allocation associated with the target to reflect the allocation of the virtual memory, all if the target does not exceed the virtual memory allocation. The method further includes waiting until the target is not exceeding the virtual memory allocation if the target exceeds the virtual memory allocation.

Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.

Abstract: An infrastructure including a cluster-global dispenser that evaluates resource consume requests against cluster-global resource management policies facilitates flexible and extensible monitoring and/or control of resource consumption for multiple and/or multi-component applications on a cluster of interconnected computers. Such an infrastructure facilitates application of comprehensive resource management to cluster computing, and compatibility with the level of abstraction offered by modern object-oriented languages. Such an infrastructure also maintains backwards-compatibility. Building on the foundation of a well-defined isolated component, the resulting resource management framework is capable of supporting a rich collection of resources and of defining policies. The notion of a cluster-global resource naturally captures the aggregation of node-local resource. This applies the familiar “single system image” attribute of cluster systems to the area of resource management.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a “pluperfect” hash function. Generally, a pluperfect hash function is a hash function that maps distinct elements in a set S to distinct hash values H with no collisions (i.e., perfect hash function) and also includes an additional constraint that the hash function does not map other elements outside the set S into the set of distinct hash values H. In some example embodiments, pluperfect hash functions are used to implement a multi-way branch statement in a computer programming language. The implementation may include generating hash values for each of the case labels of the branch statement according to a pluperfect hash function.

Abstract: A method of arbitrating data transmissions to prevent data collisions in an optical data interconnect system including a transmitting node, a plurality of receiving nodes, and one or more remaining nodes connected through an optical data channel. The method involves transmitting a transmission request signal from the transmitting node over an arbitration channel corresponding to the transmitting node, monitoring, at the transmitting node, a plurality of arbitration channels corresponding to each of the plurality of receiving nodes and the one or more remaining nodes at the transmitting node for a predetermined period of time, determining a start time for a data transmission from the transmitting node based on the monitored signals to prevent a data collision, and initiating a data transmission of a data signal from the transmitting node over the optical data channel at the determined start time.

Abstract: A method for executing a computer program involving obtaining a statement of the source code, where the statement comprises a method call, and where the source code is composed in a statically-typed programming language. The method also involves, upon entry into a loop included in the computer program: incrementing an entry counter by one; and, for each iteration of the loop, incrementing an iteration counter by one, incrementing a local counter by one to obtain an incremented value of the local counter, incrementing a summation variable by the incremented value of the local counter, and executing the iteration of the loop.

Abstract: A method for power management. The method includes gathering resource usage data for a first blade and a second blade on a blade chassis, migrating each virtual machine (VM) executing on the first blade to the second blade based on the resource usage data and a first migration policy, wherein the first migration policy defines when to condense the number of blades operating on the blade chassis, and powering down the first blade after each VM executing on the first blade is migrated from the first blade.

Abstract: A method for compiling source code, involving: obtaining a statement of the source code comprising a method call, where the source code is composed in a statically-typed programming language; determining whether the method call is a dynamic method call; upon determining that the method call is a dynamic method call, compiling a dynamic method invocation without performing type checking on the method call; upon determining that the method call is not a dynamic method call: performing type checking on the method call, selecting a target method to invoke, and compiling a static method invocation to invoke the target method.

Abstract: A method for character input, involving activating a first rotating character ribbon on a display associated with a portable electronic device, wherein the rotating character ribbon includes a first plurality of characters for selection, selecting at least one character from the first rotating character ribbon, wherein the at least one character is selected using a positioning device on the portable electronic device, and storing the at least one selected character as part of a text sequence on the portable electronic device.

Abstract: In general the invention relates to a system. The system includes processors each having a processing state. The system further includes a dispatcher operatively connected to the plurality of processors and configured to: receive a first thread to dispatch, select one of the processors to dispatch the thread to based on the processing state the processors and a power management policy, and dispatch the thread to the selected one of the plurality of processors.