Abstract: Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each one of a plurality of wafers using a semiconductor wafer fabrication process. An average yield value associated with a plurality of ICs or portions of an IC formed on each one of the plurality of wafers using the semiconductor fabrication process is determined. A transformed yield value associated with the IC or portion of an IC is generated using the actual yield value and the average yield value.

Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a . . . 301h, 302a . . . 302h), each pair of nested serpentine lines having a shared pad between them (312a . . . 312h).

Abstract: A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

Abstract: A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated circuits, comprises the steps of: estimating a representation of component mismatch from device performance measurements in a form suitable for circuit simulation; reducing the complexity of statistical simulation by performing a first level principal component or principal factor decomposition of global variation, including screening; further reducing the complexity of statistical simulation by performing a second level principal component decomposition including screening for each factor retained in the first level principal component decomposition step to represent local mismatch; and performing statistical simulation with the joint representation of global variation and local mismatch obtained in the second level principal component decomposition step.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.

Abstract: A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.

Abstract: A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Abstract: A system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle (12) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model (16). The yield model (16) embodies a layout as defined by the characterization vehicle (12) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine (18) extracts predetermined layout attributes (26) from a proposed product layout (20).

Abstract: A test vehicle has a plurality of the zig-zag structures which include: a first layer having a plurality of first elongated patterns oriented in a first direction; a second layer having a plurality of second elongated patterns oriented in a second direction substantially perpendicular to the first direction; and a plurality of vias or contacts conductively coupling ones of the first patterns to respective ones of the second patterns.

Abstract: A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.