Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: maintaining first management information for identifying a first management unit in the rewritable non-volatile memory module; collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module in a data merge operation, and the first mapping information includes logical-to-physical mapping information related to the first valid data; and storing the collected first valid data into a recycling unit.

Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.

Abstract: The disclosure provides a data storage method, a memory storage apparatus, and a memory control circuit unit. The method includes: allocating logical addresses to be mapped to physical programming units of physical erasing units; grouping the logical addresses into logical address groups; receiving write commands and data to be stored into the logical addresses; writing the data into the physical programming units; recording a data write timestamp of each of the physical erasing units; recording a bit sum of each of the logical address groups; and identifying the data belonging to the first logical address group as cold data if the bit sum of a first logical address group is less than a bit sum threshold value and the data write timestamp of the physical erasing units writing data belonging to the first logical address group is less than a timestamp threshold value.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a usage status of a first physical unit of a rewritable non-volatile memory module for storing data from a host system; determining a first rule according to the usage status; and performing a first operation according to the first rule. The first operation includes: storing a first data from the host system into the first physical unit; and storing a second data from the rewritable non-volatile memory module into a second physical unit, where the first rule corresponds to a first ratio between a data volume of the first data and a data volume of the second data. Accordingly, the memory storage device can store external and internal data stably.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.

Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: determining whether to use a first programming mode or a second programming mode to program memory cells according to a first data amount and a second data amount; when the first data amount is greater than the second data amount, programming the memory cells by using the first programming mode; and when the first data amount is not greater than the second data amount, programming the memory cells by using the second programming mode.

Abstract: A clock and data recovery circuit which includes a phase detector, a digital loop filter and a phase interpolator is provided according to an exemplary embodiment of the disclosure. The phase detector is configured to detect a phase difference between a data signal and a clock signal. The phase interpolator is configured to generate the clock signal according to an output of the digital loop filter. The digital loop filter is configured to operate automatically according a default value stored in the digital loop filter under an initial status, so as to establish a default phase shift or a default frequency difference of the clock signal with respect to the data signal before the data signal and the clock signal are compared.

Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.

Abstract: A data search method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting a boot signal; sending a first read command sequence based on a first grouping rule corresponding to grouping a first number of physical sub-units into one physical unit and then determining whether a system information of a rewritable non-volatile memory module is read; sending a second read command sequence based on a second grouping rule corresponding to grouping a second number of physical sub-units into one physical unit if the system information is not read; and operating the rewritable non-volatile memory module based on the system information. Therefore, the efficiency of searching for the system information from the rewritable non-volatile memory module can be improved.

Abstract: A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.

Abstract: A memory management method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The memory management method includes: recording sorting information corresponding to a plurality of first physical units of the rewritable non-volatile memory module according to a data storage status of the first physical units; receiving at least one command, and the command is configured to change the data storage status of the first physical units; updating the sorting information according to the command; and copying data stored in at least one physical unit among the first physical units to at least one second physical unit of the rewritable non-volatile memory module according to the updated sorting information.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.

Abstract: A mapping table updating method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: calculating a plurality of updated data counts of a plurality of updated logical units in at least one active physical erasing unit respectively according to a physical-logical mapping table; selecting a first updated logical unit from a plurality of updated logical units according to the plurality of updated data counts, and the number of the first updated logical unit is less than the number of the plurality of updated logical units; loading a first logical-physical mapping table corresponding to the first updated logical unit; and updating mapping information in the first logical-physical mapping table according to mapping information of the first updated logical unit in the physical-logical mapping table.

Abstract: A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.

Abstract: A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range; storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range; and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.

Abstract: The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.

Abstract: A universal serial bus (USB) memory is disclosed. The USB memory includes a housing having a plurality of orientated indentations and a plurality of concave props, wherein the plurality of orientated indentation facilitates the USB memory to be connected while the USB memory is inserted into a female USB socket; a print circuit board assembly (PCBA) disposed in the housing, wherein the PCBA is fixed by means of pressing of the plurality of concave props; and a LED module having a LED indicator disposed in the housing and a LED module controller disposed on the PCBA, wherein a space is formed between the housing and the PCBA for disposing the LED module.