Patents Assigned to Phison Electronics Corp.
  • Reference voltage generation circuit with reduced process variation on the reference voltage
    Patent number: 10627841
    Abstract: An exemplary embodiment of the disclosure provides a reference voltage generation circuit which includes a unit switch circuit and a voltage output circuit. The unit switch circuit is configured to receive a control voltage and generate a plurality of base voltages on a detection point inside the reference voltage generation circuit. The voltage output circuit is coupled to the unit switch circuit and is configured to modify a reference voltage for generating a specific voltage according to the base voltages. Therefore, an influence on the reference voltage due to process variation can be reduced.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 21, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Bing-Wei Yi
  • Data storage method, memory storage device and memory control circuit unit
    Patent number: 10620858
    Abstract: A data storage method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a first space in a first physical unit of a rewritable non-volatile memory module; and storing at least part of data stored in at least one physical unit of the rewritable non-volatile memory module to a second space in the first physical unit, and the second space is not belonging to the first space, and the first space is for ensuring that valid data stored in at least one second physical unit among the at least one physical unit can be stored to the first physical unit. Therefore, it is ensured that at least one spare physical unit of the memory storage device can be released by a data merging operation of multiple source nodes.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Decoding method, memory storage device and memory control circuit unit
    Patent number: 10622077
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
  • Memory management method, memory control circuit unit and memory storage apparatus
    Patent number: 10620874
    Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value. The first procedure includes: moving valid data in the physical erasing units into at least one third spare physical erasing unit; and adjusting the threshold value from a first threshold value to a second threshold value.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Horng-Sheng Yan, Kok-Yong Tan
  • DATA ACCESS METHOD, MEMORY STORAGE APPARATUS AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200097217
    Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 26, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Data merge method which reads first physical unit twice for respectively performing first stage programming operation and second stage programming operation on second physical unit, memory storage device and memory control circuit unit
    Patent number: 10592167
    Abstract: An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation; performing a first stage programming operation on the second physical unit according to the first data; reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed; and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 17, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200081653
    Abstract: An exemplary embodiment of the disclosure provides a memory management method for a rewritable non-volatile memory module. The method includes: receiving a first type command from a host system and temporarily storing the first type command to a first command queue; after receiving the first type command, receiving a second type command from the host system and temporarily storing the second type command to a second command queue; if the first command queue meets a preset condition, performing a programming operation for programming the rewritable non-volatile memory module according to the first type command in the first command queue; and after performing the programing operation, transmitting a response message corresponding to the second type command in the second command queue to the host system.
    Type: Application
    Filed: October 25, 2018
    Publication date: March 12, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chen Yap Tan
  • Data writing method, memory control circuit unit and memory storage apparatus
    Patent number: 10586596
    Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 10, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200073792
    Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
    Type: Application
    Filed: October 24, 2018
    Publication date: March 5, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Memory management method for configuring super physical units of rewritable non-volatile memory modules, memory control circuit unit and memory storage device
    Patent number: 10579289
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes recording use information according to each physical erasing unit of a rewritable non-volatile memory module. The method also includes configuring a plurality of super physical units. An address offset value corresponding to a first unavailable physical programming unit of a first physical erasing unit in a first super physical unit is the same as an address offset value corresponding to a first available physical programming unit of a second physical erasing unit in the first super physical unit.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Yen Lee
  • DATA ACCESS METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200065187
    Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 27, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • MEMORY TESTING METHOD AND MEMORY TESTING SYSTEM
    Publication number: 20200066366
    Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.
    Type: Application
    Filed: October 2, 2018
    Publication date: February 27, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Siu-Tung Lam, Chih-Hung Chiu, Kun-Tsung Lo, Chao-Kai Zhang
  • Data writing method for rewritable non-volatile memory modules based on use information, memory storage device and memory control circuit unit
    Patent number: 10564899
    Abstract: A data writing method, a memory storage device and a memory control circuit unit are provided. The data writing method includes: writing first data belonging to a first logical sub-unit of a first logical unit and second data belonging to a second logical sub-unit of the first logical unit to a first physical erasing unit and a second physical erasing unit respectively; recording use information corresponding to each logical unit; and executing a data arrangement operation corresponding to the first logical unit based on the use information of the first logical unit to copy the first data and the second data from the first physical erasing unit and the second physical erasing unit to a third physical erasing unit, wherein a logical address range of the second logical sub-unit follows a logical address range of the first logical sub-unit.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chia-Han Yen
  • Data protecting method, memory control circuit unit and memory storage apparatus
    Patent number: 10565052
    Abstract: A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Wear leveling method, memory control circuit unit and memory storage apparatus
    Patent number: 10564862
    Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • DATA MERGE METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200050399
    Abstract: An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation; performing a first stage programming operation on the second physical unit according to the first data; reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed; and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 13, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • BIT DETERMINING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200034232
    Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 30, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Siang Yang, Yu-Cheng Hsu
  • VOLTAGE ADJUSTING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200035306
    Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 30, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Szu-Wei Chen, Lih Yuarn Ou, Hsiao-Yi Lin
  • Data protecting method and memory storage device
    Patent number: 10546640
    Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
  • Memory management method, memory storage device and memory control circuit unit
    Patent number: 10545700
    Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: performing a data merge operation for at least one physical unit of the rewritable non-volatile memory module according to a write command from a host system; and adjusting times of performing the data merge operation according to a dispersion rate of a plurality of logical units corresponding to first data stored in at least one first-type physical unit of the rewritable non-volatile memory module.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 28, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Wen-Jin Li