Patents Assigned to Phison Electronics Corp.
  • Publication number: 20210064283
    Abstract: A command transmitting method, a memory control circuit unit and a memory storage device are provided. The method includes: transmitting a plurality of command sequences and a state read command sequence to a memory interface coupled to a rewritable non-volatile memory module; and storing the plurality of command sequences by the memory interface, and transmitting the state read command sequence to the rewritable non-volatile memory module.
    Type: Application
    Filed: September 29, 2019
    Publication date: March 4, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kuo-Hwa Ho, Chih-Ming Chen
  • Publication number: 20210064284
    Abstract: A memory control method is disclosed. The method includes: determining a mode for reading first data in a first management unit as a first mode or a second mode according to a data dispersion degree of the first data; reading the first data from the first management unit according to a physical distribution of the first data if the mode for reading the first data is determined as the first mode; and reading the first data from the first management unit according to a logical distribution of the first data if the mode for reading the first data is determined as the second mode. Furthermore, a memory storage device and a memory control circuit unit are also disclosed.
    Type: Application
    Filed: October 23, 2019
    Publication date: March 4, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Che-Yueh Kuo
  • Publication number: 20210064449
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: receiving at least one first read command from a host system; and determining, according to a total data amount of to-be-read data indicated by the at least one first read command, whether to start a pre-read operation. The pre-read operation is configured to pre-read data stored in at least one first logical unit, and the first logical unit is mapped to at least one physical unit.
    Type: Application
    Filed: October 4, 2019
    Publication date: March 4, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chen Yap Tan
  • Patent number: 10936248
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • Publication number: 20210056018
    Abstract: A cold area determining method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: recording a plurality of logical update counts respectively corresponding to a plurality of logical units; calculating a plurality of reference update counts respectively corresponding to the plurality of physical erasing units according to the plurality of logical update counts; calculating a reference value according to a plurality of first logical update counts respectively corresponding to a plurality of first logical units; and determining at least one first physical erasing unit belonging to a cold area among the plurality of physical erasing units according to the reference value and the plurality of reference update counts.
    Type: Application
    Filed: October 4, 2019
    Publication date: February 25, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shao-Fan Yen, Chih-Chieh Hsu
  • Publication number: 20210055756
    Abstract: A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 25, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Chien Huang
  • Publication number: 20210049064
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.
    Type: Application
    Filed: September 28, 2019
    Publication date: February 18, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Li-Chun Liang
  • Patent number: 10922021
    Abstract: The disclosure provides a data storage method, a memory storage apparatus, and a memory control circuit unit. The method includes: allocating logical addresses to be mapped to physical programming units of physical erasing units; grouping the logical addresses into logical address groups; receiving write commands and data to be stored into the logical addresses; writing the data into the physical programming units; recording a data write timestamp of each of the physical erasing units; recording a bit sum of each of the logical address groups; and identifying the data belonging to the first logical address group as cold data if the bit sum of a first logical address group is less than a bit sum threshold value and the data write timestamp of the physical erasing units writing data belonging to the first logical address group is less than a timestamp threshold value.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chang Hsieh, Che-Wei Chang
  • Patent number: 10922019
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hung Chien, Hsiao-Hsuan Yen
  • Patent number: 10923212
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Publication number: 20210027820
    Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 28, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Chien Huang
  • Publication number: 20210027824
    Abstract: A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 28, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Ming-Chien Huang
  • Patent number: 10892026
    Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20210004173
    Abstract: A data erasing method, a memory control circuit unit and a memory storage device are provided. The method includes selecting a first physical erasing unit group from a plurality of physical erasing unit groups, and performing an erase operation to the first physical erasing unit group, wherein the first physical erasing unit group includes a plurality of first physical erasing units, and the number of at least one second physical erasing unit used to perform the erasing operation at the same time point of the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.
    Type: Application
    Filed: August 22, 2019
    Publication date: January 7, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10884652
    Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 5, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10884660
    Abstract: An exemplary embodiment of the disclosure provides a memory management method for a rewritable non-volatile memory module. The method includes: receiving a first type command from a host system and temporarily storing the first type command to a first command queue; after receiving the first type command, receiving a second type command from the host system and temporarily storing the second type command to a second command queue; if the first command queue meets a preset condition, performing a programming operation for programming the rewritable non-volatile memory module according to the first type command in the first command queue; and after performing the programming operation, transmitting a response message corresponding to the second type command in the second command queue to the host system.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 5, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chen Yap Tan
  • Publication number: 20200401322
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 24, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10872656
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10871909
    Abstract: A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes writing test data to a first physical block among the plurality of physical blocks, reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; grouping the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establishing first and second block mapping tables; and mapping logical addresses of the first and second block mapping tables to the plurality of physical blocks belonging to the first and second block groups.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Siu-Tung Lam, Ming-Yen Lee, Kuo-Lung Lee
  • Patent number: 10871914
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Tai-Yuan Huang, Yi-Hsuan Lin, Chi-Shun Kao