Patents Assigned to Phison Electronics Corp.
  • Memory management method, memory storage device and memory control circuit unit
    Patent number: 10884660
    Abstract: An exemplary embodiment of the disclosure provides a memory management method for a rewritable non-volatile memory module. The method includes: receiving a first type command from a host system and temporarily storing the first type command to a first command queue; after receiving the first type command, receiving a second type command from the host system and temporarily storing the second type command to a second command queue; if the first command queue meets a preset condition, performing a programming operation for programming the rewritable non-volatile memory module according to the first type command in the first command queue; and after performing the programming operation, transmitting a response message corresponding to the second type command in the second command queue to the host system.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 5, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chen Yap Tan
  • VALID DATA MERGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS
    Publication number: 20200401322
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 24, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Data writing method, memory control circuit unit and memory storage device
    Patent number: 10872656
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Block management method, memory control circuit unit and apparatus using mapping tables and block recognition machine learning with block parameters as training data
    Patent number: 10871909
    Abstract: A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes writing test data to a first physical block among the plurality of physical blocks, reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; grouping the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks; establishing first and second block mapping tables; and mapping logical addresses of the first and second block mapping tables to the plurality of physical blocks belonging to the first and second block groups.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Siu-Tung Lam, Ming-Yen Lee, Kuo-Lung Lee
  • Memory management method, memory storage device and memory control circuit unit
    Patent number: 10871914
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Tai-Yuan Huang, Yi-Hsuan Lin, Chi-Shun Kao
  • Decoding method, memory controlling circuit unit and memory storage device
    Patent number: 10872667
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200393989
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 17, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Memory management method, memory storage device and memory control circuit unit
    Patent number: 10866887
    Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first command and performing a first operation corresponding to the first command; transmitting a completion message to a host system corresponding to a completion of the first operation; detecting command processing information; determining a transmission mode of an interruption message according to the command processing information; and transmitting the interruption message to the host system according to the transmission mode.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 15, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Hui Tseng
  • DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200388318
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 10, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200379654
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
    Type: Application
    Filed: August 2, 2019
    Publication date: December 3, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • DATA WRITING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200379676
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 3, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200371712
    Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a first data and writing the first data to at least one first physical programming unit of a first physical erasing unit; receiving a second data; temporarily storing the second data to a temporary storage area if a data length of the second data is less than a predefined value; receiving a third data; writing the third data to at least one second physical programming unit of the first physical erasing unit if a logical address storing the first data is consecutive with a logical address storing the third data; and moving the second data from the temporary storage area to at least one second physical programming unit of the first physical erasing unit if the logical address storing the first data is not consecutive with the logical address storing the third data.
    Type: Application
    Filed: July 4, 2019
    Publication date: November 26, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Yi-Hsuan Lin, Bing-Hong Wu
  • Data storing method, memory control circuit unit and memory storage device
    Patent number: 10824368
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a first write command from a host system; determining whether to write a first data corresponding to the first write command by using a first mode or write the first data by using a second mode according to an available buffer memory state; writing the first data into a first physical erasing unit among a plurality of physical erasing units by using the first mode when the first data is determined to be written by using the first mode; and writing the first data into a second physical erasing unit among the physical erasing units by using the second mode when the first data is determined to be written by using the second mode.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Method for managing association relationship of physical units between storage area and temporary area, memory control circuit unit, and memory storage apparatus
    Patent number: 10824340
    Abstract: A memory management method is provided according to an exemplary embodiment. The method includes: receiving a write command and determining whether a usage status of physical units associated to a storage area conforms to a first predetermined status; storing write data corresponding to the write command to at least one of physical units associated to a temporary area if the usage status of the physical units associated to the storage area conforms to the first predetermined status; associating the at least one physical unit storing the write data to the storage area; and allocating at least one logical unit to map the at least one physical unit associated to the storage area.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200341676
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided.
    Type: Application
    Filed: May 29, 2019
    Publication date: October 29, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chieh Yang, Yi-Hsuan Lin, Tai-Yuan Huang, Ping-Chuan Lin
  • Data merge method for rewritable non-volatile memory storage device and memory control circuit unit
    Patent number: 10810121
    Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 20, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chien-Wen Chen, Ting-Wei Lin
  • TEMPERATURE CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND TEMPERATURE CONTROL METHOD
    Publication number: 20200326736
    Abstract: A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 15, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jia-Huei Yeh, Chao-Ta Huang, Yi-Feng Li, Po-Chieh Chiu, Chun-Yu Ling
  • MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    Publication number: 20200319822
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The memory control method includes: determining a first management unit as a source block and reading valid data from a first continuous data unit in the first management unit according to first interleaving information and second interleaving information, wherein the first interleaving information reflects a total number of the first continuous data units in the first management unit, and the second interleaving information reflects a total number of second continuous data units in a second management unit; storing the valid data into a recycling block; and erasing the first management unit.
    Type: Application
    Filed: June 4, 2019
    Publication date: October 8, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Wei-Jeng Wang
  • Universal series bus connector and manufacturing method thereof
    Patent number: 10790630
    Abstract: A universal series bus (USB) connector including a base, a first terminal set, and a second terminal set and a method of manufacturing the universal series bus connector are provided. The first terminal set includes a pair of first differential signal terminals and a pair of second differential signal terminals, and terminals of the pair of first differential signal terminals are adjacent to each other and terminals of the pair of second differential signal terminals are adjacent to each other. Two of terminals of the second terminal set are located at two opposite sides of the pair of first differential signal terminals, and another two of the terminals of the second terminal set are located at two opposite sides of the pair of second differential signal terminals.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 29, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chin-Yuan Chen, Hung-I Chung, Chun-Feng Lee
  • Spread spectrum clock generator, memory storage device and signal generation method
    Patent number: 10789999
    Abstract: A spread spectrum clock generator including a clock generation circuit, an impedance component and a control circuit is provided. The impedance component is coupled to an impedance terminal of the clock generation circuit. The control circuit is configured to provide a control signal to the impedance component to generate a first voltage at the impedance terminal. The clock generation circuit is configured to generate a spread spectrum clock signal at an oscillation terminal of the clock generation circuit according to the first voltage. Furthermore, a memory storage device and a signal generation method are also provided.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 29, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kai Chang