Abstract: A substrate structure with embedded semiconductor chip and a fabrication method thereof are provided. The method includes: providing a carrier board having a first surface and an opposing second surface, wherein a first opening and an opposing second opening are formed in the first and second surfaces respectively, and a portion of the first opening communicates with the second opening; mounting at least one semiconductor chip to bottom of the first opening to be received in the first opening; filling an adhesive material in the first and second openings and in a gap between the chip and the carrier board to adhere the chip; forming a dielectric layer on the carrier board and the chip; and forming a circuit layer on the dielectric layer and forming conductive structures in the dielectric layer, so that the circuit layer is electrically connected to the chip via the conductive structures.

Abstract: A structure of a packaging substrate and a method for making the same are disclosed, wherein the structure comprises: a substrate body having a circuit layer on the surface thereof, wherein the circuit layer has a plurality of conductive pads which are each formed in a flat long shape to enhance the elasticity of circuit layout; a solder mask disposed on the substrate body and having a plurality of openings corresponding to and exposing the conductive pads, wherein the openings are each formed in a flat long shape; and a metal bump disposed in each of the openings of the solder mask and on each of the corresponding conductive pads.

Abstract: The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.

Abstract: The present invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate includes: a substrate body, having a plurality of conductive pads on the surface thereof, wherein the top surfaces of the conductive pads have a concave each; a solder mask, disposed on the surface of the substrate body and having a plurality of openings to correspondingly expose the concaves of the conductive pads each; and a plurality of metal bumps, disposed correspondingly in the openings of the solder mask and over the concaves of the conductive pads. The present invention increases the joint surface area between the metal bumps and the conductive pads so as to inhibit the joint crack and improve the reliability of the conductive structure of the packaging substrate.

Abstract: A semiconductor chip is disclosed, which comprises a chip having an active surface; plural electrode pads disposed on the active surface of the chip; a first passivation layer disposed on the chip, which has openings corresponding to the electrode pads to expose the electrode pads, wherein the first passivation layer is made of a material having high alkali resistance and low coefficient of elasticity; and plural metal bumps disposed in the openings of the first passivation layer. Therefore, as forming the metal bumps by a chemical deposition technique, the damage to the passivation layer can be prevented. Besides, as the semiconductor chip is embedded in a package structure, the problem of delamination occurred due to the mismatch in the coefficients of thermal expansion of the semiconductor chip and the dielectric layers can be avoided. Accordingly, the yield of the package structure having the semiconductor chip embedded therein can be improved.

Abstract: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A semiconductor chip-embedded circuit board and a fabrication method thereof are provided, including: a core board having first and second surfaces with first and second circuit layers thereon respectively, the first surface having a chip-receiving area (CRA); a laminated layer formed on the first and second surfaces and formed with an opening for exposing the CRA; third and fourth circuit layers formed on the laminated layer, the third circuit layer having first and second conductive pads, the fourth circuit layer having third conductive pads; a first insulating protective layer formed on the third circuit layer and formed with a plurality of first openings for exposing the first conductive pads and the CRA and a plurality of second openings for exposing the second conductive pads; and a second insulating protective layer formed on the fourth circuit layer and formed with third openings for exposing the third conductive pads. Mounting a semiconductor chip on the CRA reduces package height.

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.

Abstract: A packaging substrate structure is disclosed, which at least comprises a build-up structure including a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the first dielectric layer and the third dielectric layer. The characteristic is that the Young's modulus of the second dielectric layer is lower then the first dielectric layer and the third dielectric layer so as to form a sandwich structure of high-low-high of Young's modulus. The packaging substrate structure of the present invention can improve the quality of the product.

Abstract: A multi-chip semiconductor package structure is disclosed according to the present invention, the package structure includes: a carrier board having a first surface, a second surface, and at least an opening penetrating the first and second surfaces, the first and second surfaces each having electrically connecting pads; a semiconductor component received in the opening, the semiconductor component has a first active surface and a second active surface, and each of the first and second active surfaces has a plurality of electrode pads; a plurality of first conductive elements electrically connected to the electrically connecting pads of the first and second surfaces of the carrier board with the electrode pads of the first and second active surfaces of the semiconductor component; and a molding material formed on a portion of the first surface of the carrier board, the first active surface of the semiconductor component, a portion of the second surface of the carrier board, and the second active surface of th

Abstract: A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the

Abstract: A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for

Abstract: A multi-chip semiconductor package structure is disclosed according to the present invention.

Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads, the first circuit board comprises a first surface, an opposite second surface, a plurality of first conductive pads on the first surface, a plurality of second conductive pads on the second surface, a plurality of conductive vias, and at least one circuit layer, and the electrodes of the first chip directly electrically connect to the conductive pads on the surfaces of the circuit board through the conductive vias and the circuit layer within the circuit board; and a second package structure electrically connecting to the first package structure through a plurality of solder balls to make package on package. The stacked package module provided by this invention has characteristics of compact size, high performance, and high flexibility.

Abstract: A chip package module is disclosed, which comprises a core plate and two rigid plates individually having a circuit layer. The core plate is sandwiched in between the two rigid plates to form a composite circuit board. Furthermore, the two rigid plates individually have a cavity to expose the surface of the core plate. In addition, the cavities individually have at least one chip disposed therein, and each chip electrically connects to the composite circuit board. The present invention reduces the height of the package module and makes the package module lighter and smaller.

Abstract: A flip-chip substrate is disclosed, which comprises a core substrate including an aluminum oxide substrate and a first circuit layer, wherein the aluminum oxide substrate has a top surface, a bottom surface, and a plurality of conductive through holes, the conductive through holes connect the top surface and the bottom surface the first circuit layer disposed on the top surface and the bottom surface and electrically connects to the conductive through holes; and a built-up structure disposed on the top surface and the bottom surface and electrically connecting to the first circuit layer. Moreover, the conductive through holes are formed by forming plural through holes through electrolyzing, and then forming a first seed layer and a first metal layer inside the through holes. Therefore, the problem of substrate warpage can be prevented, and the wiring density of the flip-chip substrate can be improved.

Abstract: A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure.

Abstract: The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board to expose the inner electrode layer of the internal board. The high dielectric material layer is located on the buffer layer and the inner electrode layer. The metal layer is placed on the high dielectric material layer including an outer circuit layer capable of electrical connection to the inner circuit layer, and an outer electrode layer corresponding to the inner electrode layer to form a capacitor. Owing to the assistance of the buffer layer, the structure can enhance the transmission and the quality of the products.

Abstract: A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element.

Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.