Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.

Abstract: The invention provides a warpage-proof circuit board structure, including: an inner layer circuit board; at least one dielectric layer formed on at least one surface of the inner layer circuit board; at least one first groove formed in the at least one dielectric layer corresponding in position thereto; a solder mask formed on the surface of the dielectric layer, a second groove formed in the solder mask and corresponding in position to the first groove formed in the dielectric layer; and a metal frame formed in the first and second grooves and protruding from the surface of the solder mask, thereby strengthening the circuit board to prevent it from warping in thermal processing and further using the metal frame as a heat-dissipating means for the package structure.

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of fabricating an electrical connecting structure of a circuit board is disclosed. The method includes: providing a circuit board having a plurality of first and a plurality of second conductive pads; forming on the circuit board a solder mask having a plurality of openings to thereby expose the first and the second conductive pads; forming an metal adhesive layer on the first and the second conductive pads; forming a conductive layer on the circuit board and the metal adhesive layer; forming on the conductive layer a resistive layer, wherein a plurality of openings are formed in the resistive layer to expose the conductive layer on the second conductive pads; forming a metal post by electroplating through the conductive layer on the second conductive pads; removing the resistive layer and the conductive layer covered underneath; and forming a soldering layer on the metal post.

Abstract: A direct connection multi-chip semiconductor element structure is proposed. A plurality of semiconductor chips are mounted and supported on a metal heat sink, such that heat generated by the chips during operation can be dissipated via the heat sink. A circuit structure is extended from the chips to provide direct electrical extension for the chips and improve the electrical performances. And exposed electrical connection terminals can be formed in the circuit structure extended from the chips to be directly electrically connected to an external electronic device.

Abstract: A coreless packaging substrate and a method for making the same are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom through melting the metal adhesion layer. In addition, the disclosed packaging substrate further includes a circuit built-up structure of which has the electrical pads embedded under a surface. The disclosed packaging substrate can achieve the purposes of reducing the thickness, increasing circuit layout density, and facilitating the manufacturing of the substrate.

Abstract: A semiconductor package substrate structure includes a circuit board with a plurality of first connection pads formed on at least a surface thereof; conductive posts formed on the surfaces of the first connection pads; and an insulative protection layer formed on the surface of the circuit board and having openings formed to completely expose the conductive posts, the conductive posts protruding above the surface of the substrate, thereby the electrical connection between the conductive posts and a semiconductor chip is facilitated, and the quality and the reliability of subsequent packaging process are ensured.

Abstract: A carrier plate structure having a chip embedded therein, comprises an aluminum plate having plural through-holes extending from the upper surface to the lower surface of the aluminum plate, a cavity therein, and an aluminum oxide layer formed on the surface of the aluminum plate; a chip embedded in the cavity with an active surface having plural electrode pads set thereon; and at least one build-up structure mounted on the surface of the aluminum plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connecting to the electrode pad. Besides, a method of manufacturing a carrier plate structure having a chip embedded therein is disclosed.

Abstract: The invention provides a circuit board structure for electrical testing and a fabrication method thereof.

Abstract: A method for fabricating a conductive bump structure of a circuit board is disclosed. The circuit board with a plurality of electrical connection pads is provided. An insulating protective layer and a resist layer are successively applied on the circuit board, wherein openings are formed in the layers at positions corresponding to the pads to expose the pads. Then, a conductive layer is formed on surfaces of the resist layer and openings, and a metal layer is formed on the conductive layer via electroplating and filled in the openings. Subsequently, the metal layer and conductive layer formed on the resist layer are removed via thinning, so as to form metal bumps on the pads. After the resist layer is removed, the metal bumps are covered by an adhesive layer to form a conductive bump structure for electrically connecting the circuit board to the external electronic component.

Abstract: A package structure with circuit directly connected to semiconductor chip, which comprises: a carrier board, a semiconductor chip, and at least a built-up structure. The carrier board is formed with a through cavity therein. The semiconductor chip is mounted in the through cavity of the carrier board, and a lateral surface of the semiconductor chip is coated by an adhesive material which is not contacted by the carrier board. The built-up structure, which includes a dielectric layer, is disposed on the surface of the carrier board and an active surface of the semiconductor chip. Part surface of the dielectric layer is exposed by the through cavity. The present invention decreases warpage of the packaging structure resulting from asymmetrical built-up structures.

Abstract: A circuit board structure and a fabrication method of the same are disclosed according to the present invention. The circuit board structure includes: a carrier board with at least one surface formed with a circuit layer having electrically connecting pads; a first solder mask formed on the carrier board and the circuit layer and formed with first openings for exposing the electrically connecting pads; and a second solder mask formed on the first solder mask and formed with second openings for exposing the first openings and the electrically connecting pads. The first solder mask is made of a high-insulation photosensitive material characterized by presence or absence of impurities, such as microparticles, to have enhanced fluidity for being filled in the circuit layer, thereby preventing metal ions migration and subsequent metal hypha electricity discharge which might otherwise affect electrical performance, therefore the present invention is applicable to fine circuit fabrication.

Abstract: A circuit board structure and fabrication method thereof are disclosed, including: a circuit board with a circuit layer thereon; a reactant formed on the surface of the circuit layer, wherein the reactant is an organic metallic polymer having a polymer end and a metal ion end; and a dielectric layer formed above the reactant and the circuit board, thus forming a metallic bond between the metal ion end of the reactant and the circuit layer and forming a chemical bond between the polymer end of the reactant and the dielectric layer. Owing to enhanced bonding between the dielectric layer and the circuit board, electrical performance of the circuit board structure is improved, and the demand for fine circuits is met.

Abstract: A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the free area. A metal protecting layer is plated on the electrically connecting pads by non-plating line. The free area is removed, to form a cavity penetrating the circuit board. The present invention prevents burrs which may otherwise form on the periphery of a cavity, to increase the yield and throughput.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.

Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Abstract: A method for fabricating a thermally enhanced semiconductor device. A support plate having at least one opening is mounted on a heat sink. At least one chip is mounted on the heat sink and received in the opening. An insulating layer is formed over the chip and the support plate and filled in the opening. A plurality of vias are formed in the insulating layer to expose electrode pads on the chip. A conductive layer is deposited on the insulating layer and the exposed electrode pads. A resist layer is formed on the conductive layer and patterned to expose a predetermine part on the conductive layer. Then, a patterned circuit layer is deposited on the exposed part of the conductive layer by electroplating. The patterned resist layer and the conductive layer underneath the patterned resist layer are removed. A plurality of conductive elements are formed on the circuit layer.

Abstract: A circuit board structure with embedded electronic components includes: a carrier board having an adhesive layer with two surfaces formed with first and second metal oxide layers covered by first and second metal layers and having at least one through hole; at least one semiconductor chip received in the through hole of the carrier board; an adhesive material filling a gap between the through hole and the semiconductor chip so as to secure the semiconductor chip in position to the through hole; a high dielectric material layer formed outwardly on the second metal layer; and at least one electrode board formed outwardly on the high dielectric material layer such that a capacitance component is formed with the second metal layer, high dielectric material layer, and electrode board. Accordingly, the capacitance component is integrated into the circuit board structure.