Abstract: A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Ii are selected such that ? i = 1 j ? ? I i j closely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kth consecutive FIFO buffer write clock cycle, a Bits_Read value Ik+Ik-1 is produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.

Abstract: Multicast call blocking is reduced in TST switch fabrics with the aid of an m-entry data structure. Each entry corresponds to one of m timeslots, and has 2n sub-entries corresponding to n input ports and n output ports. An N-cast call X:(y?z1, z2 . . . zN) is representable by associating a selected entry's yth input sub-entry with z1, z2, . . . zN of the selected entry's output sub-entries. Upon receipt of a call, the data structure entries are sequentially examined to detect the first entry for which a yth input sub-entry is unused and z1, z2, . . . zN output sub-entries are unused. If such an entry is detected, the call is scheduled for transmission in the corresponding timeslot. If there is no such entry and if N=1 the call cannot be scheduled; but, if N>1 the call is divided into two or more calls and an attempt is made to schedule them as above.

Abstract: A level shifting circuit with a power monitor enable for mixed-voltage applications is described. The level shifter translates signals from a first power supply voltage domain to a second. The level shifter provides a known output state, rather than an undefined mid-rail state, when either of the power supplies for the voltage domains is not adequately powered. In addition, the level shifter is IDDQ (quiescent current) compliant when static, drawing negligible current from the power supply. The level shifter can be used with a power monitor circuit, which controls the level shifter during power-up with an enable signal.

Abstract: A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

Abstract: A loopback circuit for testing low and high frequency operation of integrated circuit transmitter and receiver components. First and second resistors forming a first branch of the circuit are series-connected between first and second circuit ports. Third and fourth resistors forming a second branch of the circuit are series-connected between third and fourth circuit ports. A DC isolator is connected between the first and second branches. At lower frequencies, the two branches are DC-isolated, enabling ATE-measurement of the transmitter's output drive level independently of the receiver, continuity testing of ESD protection structures, etc. At higher frequencies, the transmitter's output signal is split into three portions, each of which is attenuated by a selected amount. One of the attenuated signal portions is applied to the receiver to test the receiver's sensitivity, independently of possible excess resiliency in the transmitter's output drive level.

Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.

Abstract: A packet parser performs a multitude of compare and transition operations to parse through all layers of the networking protocol in accordance with which the packet is formed. The packet parser supports a plurality of packet encapsulation formats and uses directed distance graph syntax for graphical representation. At each node, the packet parser isolates and compares a packet header word with either a number of associated masked values or a number of ranges to find a match. Depending on the match, one of the arcs originating from that node, namely a source node, is selected for transitioning to a destination node. A pointer is incremented as transition from the source node to the destination node is made. The packet parser is adapted to make a transition to a destination node from any number of source nodes, one or more of which may be a destination node for others of these source nodes.

Abstract: A packet classification language (GPCL) is provided to specify protocol hierarchies among data packets in a routing device. The GPCL uses regular expressions to match incoming data packets and a syntax to describe the protocol hierarchy. A GPCL compiler produces an enhanced DFA which incorporates the regular expression for recognizing constituent parts of a data packets and which incorporates the grammar graph defining the relationships among the constituent parts. A hardware implemented DFA is used to scan the input stream which constitutes the data packets.

Abstract: A packet classification language (PCL) is provided to specify data packets in a routing device. The PCL uses regular expressions to match incoming data packets. Class identifiers associated with each regular expression identifies the class to which each recognized packet belongs for subsequent processing. A PCL compiler produces a DFA which recognizes the data packets as defined by the regular expressions. A hardware implemented DFA is used to scan the input stream which constitutes the data packets.

Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.

Abstract: Methods and apparatus for canceling pre-cursor inter-symbol interference (ISI) are disclosed. In a digital communication system, a significant amount of noise can be attributed to the pre-cursor portion of the ISI. In a receiver, it can be relatively difficult to compensate for pre-cursor ISI in part because pre-cursor ISI is a result of one or more symbols that have yet to arrive at the receiver. One embodiment removes a portion of this ISI by using multiple detection thresholds in parallel. For example, data slicing (generation of a hard decision) can include three thresholds. These thresholds for slicing include a positive offset, a negative offset and no offset. The positive and negative offsets can correspond to the expected pre-cursor component of the data channel for which the data is transmitted or to a fraction thereof. The path with the correctly-compensated ISI is selected later.

Abstract: A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192 and STS-768. The processor supports virtual concatenation with arbitrary channel mapping at both STS-1 and STS-3c granularities. The processor also supports contiguous concatenation with STS-12c, STS-24c, STS-48c, STS-192c, etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS-3c-Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation.

Abstract: An apparatus uses a “self-organizing” method to eliminate or at least partially compensate for undesired or unexpected threshold errors encountered in analog-to-digital conversions. The self-organizing feature results in a relatively good, such as an optimal, spacing of a plurality of comparator thresholds even in the presence of relatively large comparator offsets, reference offsets, or other system offsets. Advantageously, the self-organizing techniques can be used without a special starting point for the thresholds. The self-organizing techniques can be used applied to at least portions of any analog-to-digital converter ADC that uses comparators, such as flash ADCs, pipeline ADCs, and sub-ranging ADCs.

Abstract: An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double pulses in the equalized signal using known characteristics and properties of the RZ signal itself; and (c) an error calculator that generates an error signal for updating tap values based on the initial outputs of the equalizer core and the corrected outputs of the decision corrector. The decision corrector comprises a zero assertion counter that generates a clock synchronized with the timing of the received signal, and corrects the equalized signal by forcing zeroes in those portions of the equalized signal that the synchronized clock indicates should be “RZ” zeroes (as opposed to “data” zeroes or “data” symbols “1” or “?1”).

Abstract: A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference voltage and, in response, generates a control signal that controls the gain of the first and second peak detectors. Each of the first and second peak detectors optionally include a differential amplifier and a pair of common-gate amplifiers each coupled to one of the output terminals of its associated differential amplifier. An RC network may be coupled to a common terminal of the first and second common gate amplifiers of each peak detector.

Abstract: A multicast connection scheduling method for a 3-stage switch fabric with n1 first stage, n2 second stage and n3 third stage interconnected switching devices. The first and third stage devices are non-blocking for unicast connections. The center stage devices are non-blocking for multicast connections. Load tables are provided for each center stage device, with one row per first and/or third stage device. Each row represents the number of connections being serviced between the first and/or third stage devices, through the center stage device corresponding to the table. By monitoring and updating the tables, the invention derives an approximately optimal connection schedule for an input list of connection requests, such that no input connection load exceeds any center stage device's maximum input connection load capacity and no output connection load exceeds any center stage device's maximum output connection load capacity.

Abstract: A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose random access memory used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose random access memory before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides within the cache memory. The microprocessor preferably accesses the bank of general purpose random access memory using a memory mapping function which maps the memory address into a cache tag address and a cache data address.

Abstract: A method and/or system and/or apparatus for mapping a protocol including data and a limited number of control codes to an efficient encoding protocol for carrying on various other networks, particularly those with parallel processing. In specific embodiments, the invention decodes 8b/10b type data to 8b data, and then maps the data into transparent GFP frames or blocks and can further map the frames into superblocks of frames and in further embodiments add padding characters on the fly to constructed blocks to reduce buffering needed and to reduce variable delay created during frame construction.

Abstract: Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The extracted delays enables the receiver to realign the various frames of the PDH signal to reconstitute the originally transmitted signals that travel through different paths of the transport network linking the source and sink of the virtually concatenated channel.

Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.