Abstract: Methods and apparatuses for controlling transmission of converged data packets and for media access through a single next generation access (NGA) passive optical network (PON) which can coexist with EPON and GPON based systems and can interoperate with a 10 GEPON. A converged data packet is transmitted between a first node and a second node of the NGA network under NGA management control. The converged packet has a format which unifies a GEM header with the 10 GEPON preamble header and certain fields replaced in a EPON packet format to accommodate information corresponding to the preamble elements of a GEM packet. The converged data can be encoded in the line code of the 10 GEPON protocol, allowing use of a control protocol based either on MPCP or GTC for the NGA. Node apparatuses include NGA elements which enable preparation, encoding/decoding and transmission of converged packets.

Abstract: DC offsets in high-gain amplifiers should be corrected to avoid the signal distortion that would result from amplifier saturation. A predominantly digital technique is described in which a digital algorithm observes patterns in the sign of the amplifier output and drives a digital-to-analog converter (DAC), which reduces the amplifier's offset.

Abstract: The present invention discloses methods for reducing power consumption in a PON while maintaining service continuity, the method including the steps of: providing an OLT operationally connected to at least one ONU; triggering a sleep request for at least one requesting ONU; upon receiving a sleep acknowledgement, activating a sleep mode for at least one requesting ONU according to a sleep period designated in the sleep request; and terminating the sleep mode according to the sleep period. Preferably, the sleep acknowledgement is transmitted from the OLT to the requesting ONU. Preferably, the sleep period is executed by a sleep command in the sleep acknowledgement. Preferably, the method further includes the step of: upon completion of the sleep period, transmitting buffered data traffic from the OLT to a sleeping ONU. Preferably, the step of transmitting is performed without the sleeping ONU being re-registered and without causing packet reordering.

Abstract: A bus interface for transfer of SONET/SDH data that supports a plurality of SONET/SDH flows. The invention supports two line coding schemes: 8B/10B encoding of STS-12, and SONET scrambled coding for STS-12, STS-48, and STS-51. The invention additionally supports two modes of line testing: entire links can be tested by inserting and checking PRBS sequences, and the SPE payload of the largest concatenated STS-Nc which the link can carry (STS-12c, STS-48c, STS-51c) can be individually tested by inserting and checking PRBS sequences.

Abstract: A dynamic bandwidth allocation (DBA) processor comprises a DBA co-processor having DBA co-processor components and operative to perform and accelerate DBA functions, and a processing core logically coupled to the DBA co-processor through a processing bus and operative to configure and dynamically control all the DBA co-processor components and to run sections of algorithms that cannot be accelerated on the DBA co-processor. The DBA processor significantly accelerated the bandwidth allocation in a communications network such as an optical communications network or a fast wireless network. The DBA co-processor and the processing core may be integrated on a chip.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: A method for dynamic bandwidth allocation (DBA) in a passive optical network (PON) comprises the steps of: in a configuration stage, dividing a predetermined grant cycle into N parts, dividing by an optical line terminal (OLT) a plurality of optical network units (ONUs) into N ONU groups and in each cycle part, concurrently allocating grants to ONUs of one ONU group while having the ONUs of at least one other ONU group send reports and data to the OLT. In a preferred embodiment, the cycle is divided into two fixed half cycles.

Abstract: A method and architecture for the extraction of data from or the insertion of data into Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) frames is disclosed. The method and architecture provides an interface that permits the time-multiplexed data streams being extracted or inserted to have variable data-rates and no fixed alignment with respect to each other. The extraction and insertion interface accommodates for variable POH data rates and alignment inconsistencies of POH bytes amongst different paths due to floating pointer positions. The interface operates at the lowest possible frequency that can still accommodate the minimum spacing between any two consecutive words of data for a given data stream. In the insertion case, the frequency of operation chosen also allows the pipelining of requests as well as the pipelining of the subsequent associated data in response.

Abstract: Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Abstract: There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system performance requirements allow. Relatively low power dissipation occurs when the histogram of logic path delays is packed towards the critical path delay, and the critical path delay is relatively close to the system clock period. In one embodiment, power is reduced by arranging path delays to be relatively slow. In one embodiment, the histogram of path delays is shaped by establishing classes of paths based on path delay, and individually controlling the classes to slow each class down, preferably relatively close to the delay of the critical path.

Abstract: A method of managing forward error correction (FEC) initialization and auto-negotiation in ethernet passive optical networks includes receiving FEC data from an optical network unit (ONU 105), and the optical line terminal (OLT 103) responds to the ONU with FEC data. Upon receiving data not forward error corrected from an ONU. The OLT responds with data not coded for FEC (203). Similarly, upon receiving forward error corrected data from the OLT, the ONU responds with forward error corrected data (503); and upon receiving data not forward error corrected from the OLT, the ONU responds with data not forward error corrected (203). The communications quality from the ONU is monitored (501), if the communications quality is not sufficient, the OLT transmits forward error corrected data to the ONU; otherwise, the OLT transmits non-FEC data to the ONU.

Abstract: A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a given time period. If a violation is detected by any one of these three detectors, an out-of-frame signal is asserted. The incoming data stream may be a scrambled SONET or SDH data stream.

Abstract: Methods and apparatus sort integrated circuits by maximum operating speed (fmax). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for example, the set of all critical timing paths. For example, the timing can be generated by using static timing analysis (STA). The timing for a second set of critical timing paths is statistically characterized. The second set can be, for example, a sample set of critical timing paths that are measurable or are measured for a device during test. The timing can be based on STA, derived from a known good device, and the like. A device under test (DUT) is tested, and the timing for the second set of critical timing paths is determined. A fitting technique is used to fit the expected device characteristics and the measured data for the DUT, and in one embodiment, the parameters used for fitting are applied to the first set of critical timing paths, which are then used to determine an appropriate fmax for the DUT.

Abstract: The present invention is related to methods and apparatus that compensate for quadrature impairments of an analog quadrature modulator and/or demodulator over a relatively wide signal bandwidth. One embodiment pre-distorts baseband signals in a quadrature modulator compensation signal processor (QMCSP) to negate the quadrature impairment of an analog quadrature modulator and corrects a received baseband signal in a quadrature demodulator compensation signal processor (QDCSP) to cancel the quadrature impairment of an analog quadrature demodulator. The QMCSP and the QDCSP contain adaptive digital filter correction structures that pre-compensate and post-compensate, respectively, for the quadrature impairments introduced by the analog quadrature modulator and the analog quadrature demodulator over a relatively wide bandwidth.

Abstract: A method and apparatus for linearizing the gain of a common-source field effect transistor (FET) amplifier. The method involves connecting a capacitive load in parallel with the gate of the FET through a switch, and opening and closing this switch depending on the voltage on the gate of the FET. The result is a FET amplifier circuit that has a substantially linear transcapacitance characteristic, making it a useful circuit for low-distortion high-power amplifiers such as xDSL line drivers.

Abstract: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some embodiments, dedicated or configured pre-emphasis drive cells with individual enablement capability are added. In some embodiments, pull-down and pull-up cells with individual enablement capability are added to provide additional configurability options. When present, the pre-emphasis, pull-down and pull-up cells are connected in parallel across the external load to provide pre-emphasis features to the output.

Abstract: A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.

Abstract: A method of time division multiplex switching reduces the implementation area by reducing the area required for both memory storage at each egress port and the multiplexing circuitry required. Ingress and egress processors are implemented to control the storage and selection of data grains to allow for the reduction in the memory and multiplexer areas.

Abstract: A method and apparatus for building a packet grooming and aggregation engine is disclosed. The grooming and aggregation engine can be applied to the network for providing flexible aggregation and service multiplexing functions. A method and apparatus achieves the intended function that is easy to implement and easy for the network operator to manage, yet provides enough flexibility to mix and match various services at the edge node of the network. One specific embodiment of the patent is an Ethernet over SONET mapping system where user traffic is aggregated and groomed into SONET transport virtual concatenation channels.

Abstract: A method and apparatus are provided for controlling the powering-up or spin-up of devices such as hard drives using expanders in a SAS topology. The method and apparatus provides a mechanism to coordinate spin-up control among a topology of expanders. The present invention enables an expander to both process the reception of the NOTIFY command to spin up attached devices and to propagate such command to further expanders. Hierarchical spin-up control provides an advantageous, in-band mechanism that controls the expanders within the topology to limit the total number of devices powering-up at any given time.