Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.

Abstract: In a communication system in which data is transferred by packets, a ranging method in which a receiver, in a given ranging window, periodically compares received data with expected data to find a match. The periodic comparison includes searching for known preamble and/or delimiter sequences of ranging packets and involves timeouts for each search period. In case a match between the known sequences and received sequences is not found and the respective timeout is exceeded, the search and comparison process is restarted and continues until a global timeout is exceeded.

Abstract: A method for improving the bit error rate of Ethernet packets applies forward error correction (FEC) coding to transmitted packets. The FEC coding is systematic block coding, and is applied so that the coded packets can be interpreted by legacy network devices that are not capable of FEC decoding. The transmit and receive state machines of FEC-capable Ethernet nodes are modified to enable the nodes to encode and/or decode the packets with the FEC code, and to adapt the nodes' respective medium access layer (MAC) and physical layer (PHY) data rates.

Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.

Abstract: An apparatus and method are provided for equalizing a dispersive channel based on in-phase and quadrature samples corresponding to an input signal. An equalizer according to the present invention uses a novel adaptation algorithm to adjust filtering characteristics based on previous in-phase samples and a current quadrature sample. The adaptation algorithm is configured to update filter coefficients in response to detecting a transition in the in-phase samples. The equalizer provides equalization for quadrature post-cursor intersymbol interference (ISI) components of the input signal. In an embodiment, the equalizer also provides equalization for in-phase post-cursor ISI components, quadrature precursor ISI components, in-phase precursor ISI components, or a combination of the forgoing.

Abstract: Systems and methods for bandwidth doubling in an Ethernet passive optical network (EPON) enable an optical line terminal (OLT) to transmit downlink to at least one double rate optical network unit (ONU). The double rate transmission is preferably facilitated by use of single rate devices (OLT and ONU) functionally connected to provide the double rate capability. The methods include packet-by-packet multiplexing, bit-by-bit line code interleaving, doubling an inter-packet gap (IPG) length, defining windows of transmission for different transmission rates, using the 8B/10B code, removing the 8B/10B code from just the downlink transmission and symbol-by-symbol multiplexing is downlink transmissions from the double rate OLT.

Abstract: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some embodiments, dedicated or configured pre-emphasis drive cells with individual enablement capability are added. In some embodiments, pull-down and pull-up cells with individual enablement capability are added to provide additional configurability options. When present, the pre-emphasis, pull-down and pull-up cells are connected in parallel across the external load to provide pre-emphasis features to the output.

Abstract: Devices and methods for processing signals using a Burst-Mode TIA that meets EPON and GPON specifications are disclosed herein. A signal provided by a power detector is processed with the appropriate gain by using a gain selector which includes a feedback circuit to choose the gain internally, thereby eliminating the need for an external control. Further embodiments of the invention include power detectors featuring a low-pass filter, a peak detector, and/or an envelope detector. Further embodiments of the invention include a Freeze function circuit for maintaining a current gain. Further embodiments of the invention apply appropriate gains when bursts with substantially different power levels are received consecutively, and prevent the gain from being changed during a burst. In this method, a two-pole low-pass filter with an undamped response function is used.

Abstract: A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgen is less than fref. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of fref/N. An accumulator iteratively accumulates a frequency control word into a modulo-N adder and produces an accumulated value. One or more bits of the accumulated value is fed-back into the modulo-N adder for adding modulo N to the accumulated value in the next iteration. N of the modulo-N adder is the same integer as in the modulo-N counter.

Abstract: A protocol for communicating data on a passive optical network conforming to the Ethernet standard provides processes for remote network node discovery and synchronization. Uplink packet transmissions to a central controller, such as an optical line terminal, are scheduled by the central controller. Downlink packets from the central controller to a remote network node, such as an optical network unit, are encrypted to preserve privacy, and the key used for encryption is changed periodically. The protocol further provides processes for detecting the loss of physical or logical connection between the central controller and the remote network nodes.

Abstract: The invention provides a synchronizer incorporating a ?-? modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the ?-? modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block's frequency. A mapper incorporating the ?-? modulator interprets the pulse train output by the ?-? modulator as stuff/null/de-stuff commands.

Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.

Abstract: A flexible adaptation engine includes a coefficient adaptation circuit that implements multiple adaptation algorithms, and/or multiple coefficient selection algorithms, to adapt the filter coefficients of one or more digital filters, such as the transversal filters of a receiver. In one embodiment, a controller selects the filter coefficients to be adapted, and the adaptation algorithm(s) to be used to adapt the selected coefficients, based on various criteria such as convergence status data, clock recovery status signals, the current load on a processor that adapts the coefficients, and/or manual control signals. In one embodiment, the architecture supports the ability to vary the number of coefficients that are updated at a time, and to concurrently apply different adaptation algorithms to different subsets of filter coefficients. The flexible adaptation engine may be implemented in application-specific hardware and/or as a processor that executes software.

Abstract: A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

Abstract: Multi-stage networks are used for data stream permutations involving merging and demultiplexing—providing arbitrary data unit time-space interchange that can be used to solve a range of problems particularly in the field of digital data communications, particularly in digital data communication involving advanced networks for exchanging data in packets, cells, or other data units.

Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.

Abstract: A decision feedback equalizer (DFE) for a receiver that can reduce jitter is disclosed. The DFE uses an equalizer structure that employs a symbol sampling operation at a decision device, also known as a slicer. In a receiver, the phase of a signal, such as an equalized signal, is typically estimated from zero crossings in the clock recovery operation. Fluctuations in these zero crossings makes phase of the reproduced clock unstable, which decreases error performance in an associated receiver. Embodiments advantageously align inter-symbol interference (ISI) canceling terms from a feedback filter (FBF) relatively well, and thereby provide equalization of a relatively large portion of a symbol period. This advantageously stabilizes the phase of an equalized signal and reduces jitter.

Abstract: A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Abstract: A method and system for identifying faults in a passive optical network (PON), The method comprises acquiring at an optical network terminal of the PON at least one parameter indicative of at least one malfunction in at least one optical network unit of the PON, and identifying each malfunction from the at least one parameter The parameters measured include, for each ONU, laser power, sync-lock and -unlock time and bit error rates. The information at the OLT is acquired remotely and in digital form, without use of any physical probing of any point or element in the PON. The system includes a temporal measurement module and a power laser measurement module coupled to a central processing unit that can extract fault information from digital data processed in the two modules.

Abstract: A method of performing multiple parallel event accumulations. This method permits devices to implement SONET/SDH Bit Error Rate monitoring on a large number of paths, but at a significantly lower cost of implementation than would be possible using existing approaches. The method removes the need for each path being monitored to have a time reference (frame counter) of its own. Instead, each monitoring path has two accumulators whose active regions will overlap in time such that the total number of frames covered will be a power of 2. This approach allows one global frame counter to be used for all the paths in question, even if those paths have completely different accumulation periods. This method of performing BER tests allows devices to perform such operations on thousands of tributary paths (VT, TU), rather than only on the STS-n/STM-n paths that most current SONET/SDH devices support.