Patents Assigned to PMC-Sierra
  • Patent number: 7474612
    Abstract: An architecture is provided for implementing bypass, repeater and retimer functions in high-speed multi-port SERDES bypass ports and devices. Specifically, this architecture uses clock recovery to implement a repeater function which retransmits data synchronously at a recovered-clock rate, providing very low-latency as no elastic-buffers are required to perform clock-rate compensation. It also supports a full retiming function where incoming data is retransmitted synchronously to the local-clock domain, in which case elastic-buffers are needed to compensate for differences between incoming clock and local-clock domains. The architecture disclosed herein is advantageously used for Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be leveraged in other applications like Infiniband, XAUI, PCI-Express to create a single device that be used as “eye-opener” to extend reach with low-latency when operated in “repeater mode” and as retiming device when operated as “retimer-mode”.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: January 6, 2009
    Assignee: PMC- Sierra, Inc.
    Inventor: Bijit T. Patel
  • Patent number: 7471107
    Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 30, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Guillaume Fortin, Charles Roy, Mathieu Gagnon
  • Patent number: 7471739
    Abstract: The present invention is related to methods and apparatus that advantageously permit the more efficient use of an input range of an analog-to-digital converter used by an adaptive predistortion linearized RF transmitter. A main signal component of a down-converted output of an RF transmitter is removed prior to the analog-to-digital conversion of the down-converted output, thereby allowing more of the input range of the analog-to-digital converter to capture an error signal component of the down-converted output. Embodiments of the present invention can thus adaptively tune the predistortion stage to a higher degree of linearity or can use lower cost analog-to-digital converters with fewer quantization steps for the same performance.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: December 30, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Andrew S. Wright
  • Patent number: 7468974
    Abstract: A Forward Propagation Architecture is a novel switch architecture based on well-known unicast switching architectures, and provides two desirable properties: (1) no rearrangement of established calls is ever required and (2) the architecture is strictly non-blocking for multicast, even when multicast destinations are dynamically added to existing calls. These properties (excluding dynamic multicast destination addition) can be provided by standard architectures or Time:Space:Time architectures with speedup proportional to the width of the widest multicast to be supported. The speedup required by the FPA is constant and practical (approximately 4× speedup) and at significantly less hardware cost than n2 architectures. The key to the FPA's capability is a sequentially doubled fabric with a feedback loop. The FPA requires a routing algorithm for connection setting. The connection-setting algorithm is sufficiently simple to be implemented in hardware.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: December 23, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Larrie Simon Carr, Winston Ki-Cheong Mok, Kenneth Evert Sailor
  • Patent number: 7460045
    Abstract: A method and apparatus are provided for calibrating a multi-stage A/D converter, such as a pipelined A/D converter. The method and apparatus are based on estimating the bounds of histograms of codes from various stages in the A/D converter. Known approaches were effective in calibrating A/D converters but during bound estimation suffered from lock-up conditions from which it could not recover. Embodiments of the present invention describe two mechanisms for recovering from lock-up conditions and a mechanism for fast locking. If neither a gross lock-up condition nor a fine lock-up condition is detected, the estimated bound is modified based on a comparison of a current digital residue with a fast lock value and a bound window. A discontinuity in the transfer characteristic of the A/D converter can then be removed based on the estimated bound.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: December 2, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Dragos Cartina
  • Patent number: 7453954
    Abstract: The present invention is related to methods and apparatus that can advantageously reduce a peak to average signal level exhibited by single or by multicarrier multibearer waveforms. Embodiments of the invention further advantageously can manipulate the statistics of the waveform without expanding the spectral bandwidth of the allocated channels. Embodiments of the invention can be applied to either multiple carrier or single carrier systems to constrain an output signal within predetermined peak to average bounds. Advantageously, the techniques can be used to enhance the utilization of existing multicarrier RF transmitters, including those found in third generation cellular base stations. However, the peak to average power level managing techniques disclosed herein can apply to any band-limited communication system and any type of modulation. The techniques can apply to multiple signals and can apply to a wide variety of modulation schemes or combinations therof.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: November 18, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Andrew S. Wright, Richard E. Ryan, Bartholomeus T. W. Klijsen, Denis John Peregrym, Brenda Davison
  • Patent number: 7437641
    Abstract: Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: October 14, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Steven Scott Gorshe
  • Patent number: 7426679
    Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: September 16, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Steven Scott Gorshe
  • Patent number: 7424036
    Abstract: The present invention is a SONET payload processing system capable of handling virtual concatenation of SONET payloads. The payload processing system enables combinations of sub-frames, comprising an arbitrary number of virtual concatenation data streams, to be multiplexed into a single SONET frame stream. The present invention further provides a processing system that is not limited by the number of sub-frames or the grouping arrangement. The payload processing system accepts both virtual concatenation and contiguous concatenation within the same SONET frame stream and processes them into blocks of data that do not intermix information from different channels.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 9, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Thomas Alexander, David Wong, James Whitney Kimbrow
  • Publication number: 20080212560
    Abstract: Alignment-enabled secondary nodes of a DAMA network monitor the alignment of for-transmission data as it is received, and actively align the data frames into encoded blocks such that the number of blocks occupied by encoded data resulting from an unencoded datastream of a particular length is predictable rather than variable. In some embodiments, the network is an Ethernet passive optical network and the alignment includes aligning a XGMII word having a start control code to a first position in a 72 bit word input to a 66B/66B encoder, thereby encoding a start-of-frame (/S/) code to a first byte of an encoded first Ethernet 66b block.
    Type: Application
    Filed: February 6, 2008
    Publication date: September 4, 2008
    Applicant: PMC-Sierra Israel Ltd.
    Inventor: Jeff Mandin
  • Patent number: 7417985
    Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 26, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Carl Dietz McCrosky, Andrew Milton Hughes, Winston Ki-Cheong Mok, Nick Rolheiser
  • Patent number: 7415048
    Abstract: An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i.e., data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment logic stores each data word in a RAM location that is defined by an associated MFI. The data words so stored are aligned when read sequentially from their stored locations. The synchronization logic in the alignment logic synchronizes all the constituent time-slots.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 19, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Zhao Wu
  • Patent number: 7409011
    Abstract: The present invention is related to methods and apparatus that can advantageously reduce a peak to average signal level exhibited by single or by multicarrier multibearer waveforms. Embodiments of the invention further advantageously can manipulate the statistics of the waveform without expanding the spectral bandwidth of the allocated channels. Embodiments of the invention can be applied to either multiple carrier or single carrier systems to constrain an output signal within predetermined peak to average bounds. Advantageously, the techniques can be used to enhance the utilization of existing multicarrier RF transmitters, including those found in third generation cellular base stations. However, the peak to average power level managing techniques disclosed herein can apply to any band-limited communication system and any type of modulation. The techniques can apply to multiple signals and can apply to a wide variety of modulation schemes or combinations thereof.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: August 5, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Andrew S. Wright, Richard E. Ryan, Bartholomeus T. W. Klijsen, Denis John Peregrym, Brenda Davison
  • Patent number: 7401272
    Abstract: A test method allows testing of source-synchronous high-speed wide busses on automatic testing equipment for at-speed characterization and production at-speed testing. An integrated circuit that is verified using the method and systems including such an integrated circuit are also disclosed. The invention can enable sampling or testing of signals or test pins that that are running very fast, particular compared to available automatic testing equipment for testing these device. The invention uses data recovery emulation on various types of automated test equipment to capture output data for further, more sophisticated analysis.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 15, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Gershom Birk, Kenneth William Ferguson
  • Patent number: 7394828
    Abstract: A data format conversion method and apparatus are presented to convert time-slot interleaved SONET/SDH data to per time-slot data for virtual concatenation processing. The converter consists of an input buffer and a matrix transposer. The input buffer discards the overhead and fixed stuff bytes of each SPE that it receives, while the matrix transposer packs the N payload bytes into N-byte words with alignment to a start-of-frame indicator. Because each N-byte word is associated with a different time slot, the N-byte words form per time-slot data.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 1, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Zhao Wu
  • Patent number: 7391787
    Abstract: A method and system are provided for opportunistic request-grant switching. If an ingress has no granted payload segment to send, and a flow exists which requires a request to be sent, an opportunistic payload segment is sent including a request and a payload segment related to the request. If an opportunistic payload segment is sent and the payload is dropped, the request is kept and is then treated as a regular request-grant request. The ingress port consequently only has to transmit the payload a maximum of twice. Ingress ports can thus opportunistically exploit the low latency available when egress ports are not contended for, and yet fall back on the strong fairness and quality of service (QoS) assurances of request-grant semantics. Buffering in the switch core can optionally be implemented to extend performance gains, but fairness and QoS are not dependent on this buffering.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 24, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Carl Dietz McCrosky
  • Patent number: 7388937
    Abstract: Systems and methods for analyzing the jitter content of an oversampled digital communication signal are disclosed. Advantageously, the communication signal can correspond to an arbitrary data sequence, rather than only to a repeating test sequence. For example, the systems and methods can be embodied in test equipment and in simulation equipment as design tools and/or validation tools. The systems and methods disclosed advantageously facilitate the decomposition and quantification of the main jitter components (random and deterministic), as well as its various subcomponents (periodic jitter, data-dependent jitter, inter-symbol interference, device-state-dependent jitter, other bounded uncorrelated jitter, and data-dependent-random jitter).
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: June 17, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Kevin L. Rodger, Kenneth W. Ferguson, Kevin Chun Yeung Hung, Jeremy Paul James Benson, Andrew S. Wright
  • Patent number: 7363563
    Abstract: Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transmitting data. This permits data tracking circuitry of a receiver to be efficiently tested with a relatively simple loop back test.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: April 22, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Jurgen Hissen, Brett Clark, Stephen Hiroshi Dick, Chris Siu
  • Patent number: 7353446
    Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: April 1, 2008
    Assignee: PMC-Sierra, Inc.
    Inventor: Steven Scott Gorshe
  • Patent number: 7349424
    Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: March 25, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: George Apostol, Jr., Mahadev S. Kolluru, Tom Vu