Abstract: An encapsulating composition and a semiconductor package are provided. The encapsulating composition adapted to encapsulate a semiconductor die includes a photosensitive dielectric material and a polarizable compound suspended in the photosensitive dielectric material. The polarizable compound within a predetermined region of the encapsulating composition affected by an external stimulus is arranged uniformly in a thickness direction to provide a conductive path penetrating through the photosensitive dielectric material along the thickness direction. The semiconductor package includes the encapsulating composition encapsulating the semiconductor die, a first and a second redistribution layer. The first and the second redistribution layer disposed on the opposite sides of the encapsulating composition are electrically connected each other through the encapsulating composition. A manufacturing method of the semiconductor package is also provided.

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.

Abstract: A manufacturing method of a semiconductor package structure is provided. The method includes the following steps. A first redistribution layer is formed on a first surface of a semiconductor substrate. A plurality of through holes and an opening are formed on the semiconductor substrate. A chip is disposed in the opening of the semiconductor substrate. A conductive through via is formed in the through holes to electrically connect the first redistribution layer. A second redistribution layer is formed on a second surface of the semiconductor substrate opposite to the first surface to electrically connect the chip. The second redistribution layer is electrically connected to the first redistribution layer by the conductive through via. A plurality of conductive structures are formed on the second redistribution layer. A semiconductor package structure is also provided.

Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.

Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.

Abstract: A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. The conductive pillars are disposed on the pads, wherein each of the conductive pillars is a solid cylinder including a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface. The encapsulant encapsulates the semiconductor component and the conductive pillars, wherein the encapsulant exposes the top surface of each of the conductive pillars. The redistribution layer is disposed on the encapsulant and electrically connected to the conductive pillars.

Abstract: A package structure includes a redistribution structure, a die, an insulation encapsulation, a protection layer, and a plurality of conductive terminals. The redistribution structure has a first surface and a second surface opposite to the first surface. The die is electrically connected to the redistribution structure. The die has an active surface, a rear surface opposite to the active surface, and lateral sides between the active surface and the rear surface. The insulation encapsulation encapsulates lateral sides of the die and the first surface of the redistribution structure. The protection layer is disposed on the rear surface of the die and the insulation encapsulation. The conductive terminals are formed on the second surface of the redistribution structure.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.

Abstract: A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Abstract: A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.

Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

Abstract: A conductive layer is formed on a first surface of a first carrier. The redistribution layer is formed on the conductive layer. Then an open-test is performed to the redistribution layer. Since the conductive layer and the redistribution layer constitute a closed loop, a load should be presented during the open-test if the redistribution layer is formed correctly. After the open-test is performed, the first carrier and the conductive layer are removed. Then a short-test is performed to the redistribution layer. No load is presented during the short-test if the redistribution layer is formed correctly since the redistribution layer constitutes an open loop. Therefore, whether the redistribution layer has flaws can be determined before the dies are boned on the redistribution layer. Thus, no waste of the good die occurs because of the flawed redistribution layer.

Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Abstract: An image sensor including a device chip, a plurality of spacers, a dam layer, a lid, and a plurality of conductive terminals. The device chip has a first surface and a second surface opposite to the first surface. The device chip includes a sensing area on the first surface and a plurality of conductive pads surrounding the sensing area. The spacers are over the first surface of the device chip. The dam layer encapsulates the conductive pads and the spacers. The lid is over the dam layer. The conductive terminals are over the second surface of the device chip and are electrically connected to the conductive pads. In addition, a manufacturing method of the image sensor is also provided.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.