Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: There is disclosed a reduced-scale digital data deinterleaver of simple structure. In a preferred embodiment each word is comprised of 32 bits of data, and 32 words form a block. In each block, each word is separated into four phases cyclically. The resulting bit lines and word lines are interchanged to produce interleaved data items. One block of the interleaved data items is written into a RAM. A higher significant address of 5 bits and a lower significant address of 5 bits of the RAM are specified by the higher significant 5 bits and the lower significant 5 bits, respectively, of the output from a counter. Whenever a block of data is written to the RAM the higher significant 5 bits and the lower significant 5 bits are interchanged to produce first and second count signals. Data is read from the specified address, 1 bit at a time and data is written, 1 bit at a time, into the address just from which data was read out.

Abstract: A CMOS inverter capable of operating at low voltages is provided. The gate of a p-channel MOS transistor and the gate of an n-channel MOS transistor are AC coupled to an input terminal via first and second capacitors, respectively. Signals whose amplitude centers are optimized according to the threshold voltages of the p- and n-channel MOS transistors by bias voltages from first and second variable voltage sources, respectively, are supplied to the gates of these MOS transistors. In consequence, the CMOS inverter can operate at high speeds at low power supply voltages without being affected by the threshold voltages.

Abstract: A temperature compensated oscillator keeping the area of a capacitor array and the bit number of a memory from increasing and allowing for high precision is provided. A adjusting method of such a resonator and an integrated circuit for temperature compensated oscillation are also provided. A capacitor array and a variable capacitance diode are connected and used as a load capacitance in an oscillation circuit, and the capacitance value of the former is digital-controlled and that of the latter is analog-controlled, so that the amount of compensation data necessary for the digital control is reduced and highly precise temperature compensation is permitted.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: A ferroelectric body transistor having a structure of MFMIS (conductor film) -ferroelectric film-conductor film-insulating film-semiconductor) including a gate insulator capacitor having an MIS structure, a low dielectric constant layer restraining layer interposed between an insulating film made of a material having a high inductive capacity of CeO2 and a semiconductor substrate to thereby restrain a low dielectric constant layer of SiO2 or the like from being produced at an interface between the insulating film and the semiconductor substrate and restrain a capacitance from being reduced. An area of the gate insulator capacitor can be reduced and highly integrated formation is provided.

Abstract: A semiconductor temperature detecting circuit use semiconductor temperature sensors each comprising bipolar transistors connected in a Darlington connection to provide a semiconductor temperature detecting circuit capable of automatically compensating for variations in fabrication of a reference voltage for comparing outputs of temperature sensors. The semiconductor temperature detecting circuit includes a first and a second semiconductor temperature sensor each having bipolar transistors connected in Darlington connection and respectively receiving different constant currents (I and nxI). Temperature detected is based on a corresponding relationship between a ratio of output voltages of the first and the second semiconductor temperature sensors and the temperature.

Abstract: A neutralization of an equivalent parallel capacitor of a piezoelectric resonator is realized to obtain a stable activation of oscillation and secure a large frequency variation. A crystal resonator is connected between an input and output terminals of an inverting amplifier to form a Colpitts-type oscillator circuit, an input terminal of another inverting amplifier is connected to the output terminal through a capacitor and the output terminal is connected to the input terminal through another capacitor to form a Miller capacitor circuit for electrically neutralizing a parallel capacitor existing equivalently between both sides of the crystal resonator.

Abstract: To provide a voltage controlled oscillator having a large variable width of oscillation frequency while ensuring oscillation starting performance, a P-channel MOS transistor Tr is made ON by detecting that an oscillation signal is provided with a predetermined amplitude value and oscillating operation is shifted from an initial state to a steady state by a detecting circuit OPC and a capacitor CA is connected in series with a series circuit constituted by a crystal resonator XL and a varicap diode CV. In the initial state, a load capacitance is reduced to thereby cancel an amount of reducing conductance gm of an oscillation amplifying portion to correspond to operation of the crystal resonator by a low amplitude and negative resistance necessary for maintaining excellent oscillation starting performance is provided and in the steady state, a width of changing the oscillation frequency is enlarged by enhancing an effect of the varicap diode CV.

Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.

Abstract: Display device designed to prevent surroundings from being adversely affected by noise includes an inner circuit board on which a support frame is mounted in a specific position. A liquid crystal panel is mounted on the support frame and held stationary by a frame. An EL panel for illuminating the liquid crystal panel is mounted behind the liquid crystal panel. An EL circuit board holding an EL driver circuit thereon is bonded to the bottom surface of the EL panel. A shielding plate is mounted on a top surface of the inner circuit board surrounded by the support frame, and is located opposite the EL panel. The shielding plate cuts off noise generated by the EL driver circuit. The EL panel is connected with electrodes on the EL circuit board via lead wires. An electrode on the EL circuit board and an electrode on the circuit board are connected via a contact member. Electric power and control signals are supplied via this contact member.

Abstract: A fractional-N frequency synthesizer is offered which does not produce spurious signals of periodically conspicuous spectral intensities and can cancel produced spurious signals up to a practical level even with a spurious-canceling circuit of low accuracy. The synthesizer has a sigma-delta noise shaper. The integral and fractional parts of a frequency divide ratio-setting value that frequency-divides the output signal are set. The fractional part of the frequency divide ratio-setting value is applied to the sigma-delta noise shaper every phase comparison period. The output from the noise shaper and the integral part of the frequency divide ratio-setting value are summed up to thereby produce a sum. The output signal is frequency-divided, using this sum as a frequency divide ratio. The difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is produced and accumulated in an accumulator every phase comparison period.

Abstract: A highly efficient charge pump circuit featuring easy circuit design and formation as well as high reliability includes transistors M1-M4 individually having a diode connection configuration and interconnected in cascade, and is adapted to alternately apply a clock signal and an inverted clock signal to the transistors via capacitor elements C1-C4. The charge pump employs a depression-type transistor as the transistors M1-M4 and has an arrangement wherein the transistors M1, M2 on an input side have a greater gate length than the succeeding transistors M3, M4 for increasing the efficiency of boosting voltage. The charge pump circuit includes a single type of device so as to facilitate the circuit design and formation and also to enhance the reliability thereof.

Abstract: A current control circuit for maintaining constant current characteristics with respect to power source potential fluctuations has a first resistor with one end connected to a source potential first and second P-channel field effect transistors each having a source connected to the other end of the first resistor and a gate coupled to a gate of the other P-channel FET. The first P-channel FET has a drain directly connected to the mutually coupled gates. A second resistor connects a drain of the second P-channel FET to the mutually coupled gates, and a resistor element connects the mutually coupled gates to a zero potential. A voltage arising at the drain of the second P-channel FET is used as a gate-driving voltage for driving a gate of a current-setting transistor.

Abstract: In a delta sigma type D/A converter, in order to be capable of carrying out muting operation in steps at steps lower than 1 quantized step by digital processing, a multiplexor 2 for selectively outputting a mute code 15 for making an analog signal null and a thermometer code 14 to a local DAC4 is provided between a thermometer code converter 1 and the local DAC4, a time period of 1/M of a sampling period is made to constitute 1 cycle, at m1 (0≦m1≦M) cycle, the thermometer code 14 is made an output of the multiplexor 2 and at other m2 (m2=M−m1) cycle, the mute code 15 is made an output thereof and muting is carried out reducing the m1 cycle or muting is relieved by increasing thereof in steps at respective sampling period.

Abstract: Ferroelectric memory element having an MFIS structure including a silicon semiconductor substrate and an insulating film arranged above the silicon semiconductor substrate. The insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film so that an unnecessary, low dielectric constant layer is prevented from forming between the semiconductor substrate and the insulating film. A ferroelectric film is arranged on the insulating film. The low dielectric constant layer restraining film is thinner than the ferroelectric film.

Abstract: To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: Automatic slice level control response to differential input signals is provided to remove in-phase noise and effects on S/N ratio Analog differential input signals Vinp and Vinn are inverted with respect to each other and applied to input terminals in1 and in2 of a comparator via resistors R1 and R2. A data stream is provided giving DSV=0. A charge pump is driven by a digital signal from the comparator. A transconductance amplifier produces output current Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump and a reference voltage Vref. The output currents are supplied to the input terminals in1 and in2 of the comparator to provide a DSV=0.

Abstract: A drive circuit capable of adjusting a capacitive load operation, for example, respective brightness of an electroluminescence (EL) element. The drive circuit is a constant current drive system and causes a plurality of capacitive loads, for example, EL elements, to emit light. This is done by setting a coil drive signal applied to the gate of a transistor Tr1. The transistor generates a surge pulse by intermittently connecting a direct current power source to a coil L1 of a step-up circuit 1. The coil drive signal is set to a frequency in accordance with an EL element as a capacitive load driven alone or a combination of EL elements simultaneously driven. Power generated by the step-up circuit 1 can be selected, brightness of a driven EL element E1 or E2 can individually be set or brightness of the EL elements E1 and E2 simultaneously driven can be set.