Abstract: A crystal oscillator circuit includes a CMOS invertor having an input terminal and an output terminal, a crystal resonator connected between the input terminal and the output terminal respectively at a first connection node and a second connection node, and a feedback resistor connected between the input terminal and the output terminal of the CMOS invertor. A first capacitor is provided between the first connection node and a power source terminal at a predetermined potential and a second capacitor is provided between the second connection node and a power source terminal at the predetermined potential. At least one resistor is disposed in series with at least one of the first capacitor and the second capacitor and has a resistance so as to limit a crystal current in the crystal resonator while maintaining negative resistance for stable oscillation. In an embodiment, a resistor is provided in series with each capacitor.

Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.

Abstract: To provide a method of fabricating a MOS-type transistor of a LDD structure with a gate electrode made of molybdenum, which brings about a reduction in the amount of overlapping between the gate electrode and source/drain, a gate electrode is made of molybdenum and forms a first pattern. The first pattern is subject to nitriding process to form a second pattern. The second pattern includes an interior electrode layer and a nitride layer located outside of the electrode layer. The thickness of the nitride layer corresponds to the amount of overlapping between the second pattern and source/drain.

Abstract: Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from constant current sources Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 receive an electric current from a constant current source Cs3 and have their respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on.

Abstract: There is disclosed a variable-gain circuit forming resistors on a semiconductor substrate. The ratio of the total resistance to the minimum resistance is made smaller than heretofore. The circuit is miniaturized. The variable-gain circuit comprises an operational amplifier, a first set of resistors R1-Rn+1, a second set of resistors Rx1-Rxm, switches SW1-SWn and a control circuit. This control circuit closes only one of the switches SW1-SWn at all times.

Abstract: An electrostatic protection circuit of a semiconductor device comprises a first MOS transistor of specific conductive type and a second MOS transistor of the specific conductive type. In the first MOS transistor, a drain thereof is connected to an output terminal or an input terminal and a source thereof is connected to a first power terminal and the first MOS transistor is controlled to be on/off by a signal received by a gate or ordinarily turned off by holding the gate at a specific potential. In the second MOS transistor of the specific conductive type, a drain thereof is connected to the output terminal or the input terminal and a source thereof is connected to a gate of the first MOS transistor and the second MOS transistor is ordinarily turned off by connecting a gate thereof to the first power terminal.

Abstract: The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.

Abstract: There is disclosed a frequency divider that operates at an improved operating speed and provides frequency division given with a frequency division ratio of N, where N is an odd number. The frequency divider comprises first, second, and third stages of D-type flip-flops. The first stage selects either the output from the second stage or the output from the third stage according to the logic level of the output from the third stage. Delay is eliminated from between the first and third stages and from between the first and second stages. Consequently, the operating frequency can be enhanced.

Abstract: A digital data processing circuit has an inverting circuit for inverting a positive/negative sign of the output data of an encoding circuit. A correcting circuit returns the inverted sign of the data to an original sign of data after decoding. Offset is made for truncation noises caused by the respective filtering operations in the encoding circuit and said decoding circuit. Sound quality is suppressed from degrading without increasing the circuit scale.

Abstract: There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.

Abstract: An oscillation circuit that improves the duty controllability by cross-coupling ring oscillators that are comprised of current inverters. The sources of current supply circuits 4a-4c and 6a-6c are connected to a power supply and their drains are connected to terminals A in corresponding current inverters, respectively. Each of the gates of those current supply circuits receives an output of a current inverter corresponding, one to one, to a current inverter to which the current supply circuit is connected.

Abstract: To provide a semiconductor device and a method of making a semiconductor device capable of preventing exfoliation at a pad electrode portion, a barrier metal layer 14, a silicon layer 15 and an aluminum layer 16 are formed on a side of a main face of a silicon substrate 11 (step A), the barrier metal layer 14, the silicon layer 15 and the aluminum layer 16 are patterned into a shape of a pad electrode (step B) and a silicide layer 17 is formed by an annealing treatment successive to the patterning step (step C).

Abstract: A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates.

Abstract: A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency.

Abstract: An IC testing apparatus has a detecting circuit for detecting an inversion of an output state of a test output from an IC under test in response to application of a clock signal, a comparing circuit for comparing a value preset in a storage circuit with the output state of the test output and an output state of the detecting circuit. In a first comparison operation, the number of pulses of the clock signal applied to the IC under test is less than the number of pulses required to invert the output state of the test output by one pulse and the test output and detector output are compared with corresponding values preset in the storage circuit at times coincident with a test strobe signal synchronized with the clock signal. In a second comparison operation, another clock pulse is applied to the IC under test to make the total number of pulses equal to that needed for inverting the test output and the above comparisons are again made with corresponding preset values.

Abstract: A digital audio recorder and system efficiently increases a sampling frequency and a number of bits of a digital audio recording. The digital audio system has a frequency analyzer receives a first digital waveform data having a sampling frequency fs1 and N1 number of bits and determining a sampling frequency fs2 in accordance with a highest frequency component of the first digital waveform data. A delay device delays the first digital waveform data a time period equal to the time required for the frequency analyzer to determine the highest frequency component and then sends the first digitial waveform data to a frequency converter. The frequency converter converts the first digital waveform data to a second digital waveform data having the sampling frequency fs2 and a number of bits N2.

Abstract: A phase comparator has a first comparing circuit and a second comparing circuit. The first comparing circuit produces a first output pulse having a duration equal to a phase lead of a first input signal with respect to a phase of a second input signal. The first phase comparator also produces a second output pulse equal in duration to a phase lag of the first input signal with respect to the phase of the second input signal. The second comparing circuit produces a third pulse equal in duration to a phase lead of a third input signal with respect to a phase of a fourth input signal. The second comparator also produces a fourth output pulse equal in duration to a phase lag of the third input signal with respect to the phase of the fourth input signal.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: A transferred data recovery apparatus capable of recovering transferred data from a transferred data signal has a first comparator for comparing transferred data signal with a reference level R to output binary-quantized data signal representing whether or not the transferred data signal is higher than the reference level R. A sample and hold circuit is driven by a clock signal and samples the binary quantized data signal each clock period to output sampled digital data to an averaging circuit. The averaging circuit sequentially averages a predetermined number of the sampled digital data each clock period to produced averaged outputs. A second comparing circuit digitally compares the averaged outputs against an upper reference level and a lower reference level dependent upon the direction of change to produce a recovered data output. The recovered data output goes low when the averaged output goes lower than the lower reference level and goes high when the averaged output goes above the upper reference level.

Abstract: In an APC system waveform dam compression apparatus which generates an optimum prediction coefficient utilizing a block calculation process in a first mode and generating prediction data utilizing a block calculation process based on this optimum prediction coefficient in a second mode with respect to a fixed number of blocked waveform data, to make possible use of suitable data in the first prediction calculation process of each block calculation process. A data holding section for holding data corresponding to at least final first waveform data to be used in a final prediction calculation process of a block calculation process in a second mode, and a first selection section for using data held in the data holding section in place of data memorized in a second delay section in each first prediction calculation process of each block calculation process of the next block are provided in an operating circuit.