Abstract: A pole-shifted noise shaper whose transfer function has a Z-plane in which the pole has been shifted out of the origin. The noise shaper suppresses idle pattern. The noise shaper has a dither adder (17) placed immediately before a quantizer (16) to add a dither signal to data about to be applied to the quantizer (16). This suppresses attenuation of the dither signal due to noise shaping. Therefore, the dither signal can be supplied effectively. The idle pattern appearing in the output signal can be suppressed. Since the pattern of the dither signal is varied at a frequency that is {fraction (1/16)} to ⅛ of the frequency of the operating clock signal, the frequency of noise component due to the dither signal lowers. The signal and the dither signal component can be easily separated in a rear stage.

Abstract: A temperature compensated oscillator has a frequency comparing circuit for comparing a frequency of an oscillating output signal of an oscillator circuit and a frequency of an external reference frequency signal externally inputted, and also has a sequential comparing register for determining each bit of a compensation datum based on this comparison. A digital signal from the sequential comparing register is applied to an input of a D/A converter for generating a control voltage of a varicap diode. The temperature compensated oscillator performs a self compensating operation for sequentially determining each bit of the sequential comparing register every frequency comparison, and conforming the frequency of the oscillating output signal to that of, the external reference frequency signal. The digital signal from the sequential comparing register is stored as compensating data corresponding to a detecting temperature of a temperature detector at that time.

Abstract: MOS semiconductor device including a substrate having source and drain regions laterally spaced from one another and a channel therebetween, a gate electrode over the channel and an oxide layer. The oxide layer includes a gate oxide layer between the gate electrode and the substrate, an oxide film having a having a thickness greater than a thickness of the gate oxide layer and a boundary oxide layer between the gate oxide layer and oxide film. The boundary oxide layer has a thickness between the thickness of the gate oxide layer and the thickness of the oxide film. The oxide film boundary oxide layer are formed by selective oxidation before formation of the gate electrode. The gate electrode has end portions extending over a portion of the oxide film while receiving no distortion from the boundary oxide layer to thereby improve breakdown voltage performance at the end portions of the gate electrode.

Abstract: To provide a cascode amplifying circuit having large amplifying gain without narrowing an output operational range or deteriorating response performance of the circuit even with a constitution by a small number of elements is achieved by applying negative feedback from the source to the gate of an MOS transistor M2 provided with an output terminal at the drain via the source and the drain of an MOS transistor M3 of N-channel type, the source and the drain of an MOS transistor M4 of P-channel type and a current mirror constituted by MOS transistors M5 and M6 of N-channel type. By this constitution, operation of the MOS transistor M3 is not effected with influence of lowering of voltage of the source of the MOS transistor M2, a wide output operational range is provided and mirror effect with respect to gate/drain capacitance of the MOS transistor is restrained to thereby restrain a reduction in response speed.

Abstract: To make compatible low consumption power formation of a control circuit of a light emitting element and high frequency formation of operational frequency band constituting a variety of usable combination elements of light emitting elements and light receiving elements, bias current is provided to a current mirror for dividing monitor current of a photodiode PD1 by a current source to thereby compensate drive function of a post stage in driving thereof by low current. Reference voltage of a current-voltage conversion portion is set in accordance with an input range of an operational amplifier of a gain adjusting portion at a post stage and input to the operational amplifier is fitted to an input range optimizing amplifying function. There are provided switching circuits SW1 and SW2 for selectively supplying monitor current from two photodiodes to respective APC loops of laser diodes LD1 and LD2 to thereby deal with a 2LD-1PD element and two of 1LD-1PD elements.

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow.

Abstract: To provide an amplifier excellent in temperature characteristic and providing an output signal having small crossover distortion in a wide power source voltage range, voltage values provided to positive phase input terminals of a second and a third amplifier 2 and 3 are made to correspond to voltages between sources and drains of a second P-channel MOS transistor Tr3 and a second N-channel MOS transistor Tr4, a first P-channel MOS transistor Tr1 and a first N-channel MOS transistor Tr2 constituting a power buffer 4, are driven by an output signal of a first operational amplifier 1 via the second and the third amplifiers 2 and 3 and therefore, there can be provided idling currents independently from power source voltage from low power source voltage, there can be provided an output signal having small crossover distortion in a wide power source voltage range and temperature dependency thereof can be improved.

Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.

Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.

Abstract: Automatic slice level control in response to differential input signals is enabled. Analog signals are transferred differentially to remove in-phase noise. Thus, its effects on S/N are alleviated. Ideal desired DSV (e.g., DSV=0) is accomplished. Also, the circuit scale is reduced, and the processing speed is enhanced. Analog differential input signals vinp and Vinn which are obtained by reading a recording medium and are inverted with respect to each other are supplied to input terminals in1 and in2 of a comparator (1) via resistors R1 and R2. A data stream is recorded on the recording medium while giving DSV=0. A charge pump (2) is driven by the digital signal from the comparator (1). A transconductance amplifier produces output currents Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump (2) and a reference voltage Vref.

Abstract: In a capacitive load drive circuit, in order to bring an output terminal used for supplying a drive voltage to a non-selected capacitive load into a high impedance state and in order to prevent the capacitive load from being unnecessarily driven by electric charge flowing to parasitic diodes at the output terminal, such as to prevent a non-selected electroluminescence element from turning on, a synchronizing unit generates second selecting signals by synchronizing first selecting signals to a clock signal constituting a basis of a drive signal of a common inverter for generating drive voltage to a common output terminal of plural electroluminescence elements, a drive signal generating unit brings individual output terminals into the high impedance state based thereon and a timing thereof is synchronized to a timing at which a potential difference between two poles of the non-selected electroluminescence element is nullified.

Abstract: The problem of the present invention is, in a plural-number order delta sigma D/A converter, not to cause click noise upon performing mute operation at no-signal input idling and hence to eliminate the necessity of a circuit for removing this. In order to perform sequence operation for rendering zero an output signal by lowering the order of a loop filter in order when stopping the operation of a plural-number order delta sigma D/A converter, 1st-order differentiators corresponding to each order and switch means for rendering inputs to these 1st-order differentiators zero are provided in the loop filter.

Abstract: A syndrome computing apparatus includes first syndrome computing circuit 2, 4 for receiving a predetermined number of bits of data (codewords) encoded based on a predetermined generator polynomial and performing a syndrome computation on the data inputted based on the generator polynomial. Shift register 1 delays the data by the predetermined number of bits. Second syndrome computing circuit 3, 5 receives the data delayed by the predetermined number of bits, and performs a syndrome computation on the data inputted based on the generator polynomial. Operating circuit 7, 8 vector-adds modulo 2 a first syndrome outputted by said first syndrome computing means to a second syndrome outputted by said second syndrome computing means. Outputs of said operating means 6, 7 are offered as a syndrome based on the generator polynomial.

Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.

Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10&OHgr; to 320&OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.

Abstract: An improved delta sigma digital-to-analog converter in which the thermometer code, which is output from a thermometer code converter, is divided into P blocks for every Q bits. An arrangement of the blocks is shifted in rotation by a barrel shifter at a frequency fs. Along with this, an arrangement of bits within each block is shifted in rotation by a shift register at a frequency of Q times fs. The bits within the code thus obtained are provided to local DACs, each specified to correspond to each of the given bits. In this manner, it is possible to maintain a lower operating frequency while at the same time to reducing the distortion in the output caused by a change in shifting the data in rotation in the local DACs, which change occurs depending on bit levels of the data in a form of the thermometer code.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inveter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption.

Abstract: A delta-sigma D/A converter has a quantizer, a thermometer code converter portion, and an odd/even bit-interchanging portion. The quantizer produces a first digital signal. The thermometer code converter portion and odd/even bit-interchanging portion divide the output level of the first digital signal such that it is represented by the sum of the output levels of second and third digital signals. Each of the second and third digital signals has an output level obtained by dividing the output level of the first digital signal by a factor of 2 or an integer close to it. During the former half of each sampling interval, first and second adders produce, respectively, a level signal corresponding to the second digital signal and an inverted level signal corresponding to an inversion of the third digital signal.

Abstract: There is provided a D-type flip-flop circuit which is improved in terms of operating frequency. First and second current supplying circuits are provided as sources for supplying currents to first and third differential circuits for inputting data and to second and fourth differential circuits for holding data in a master circuit and a slave circuit. Further, timing for supplying the currents to the respective differential circuits for inputting and holding data are controlled by first and second clock signals, respectively. The D-type flip-flop circuit is improved in terms of operating frequency by optimizing timing for writing input data and timing for holding data by arranging the first clock signal so as to have a certain delay with respect to the second clock signal. Further, the D-type flip-flop circuit is improved with respect to the operating frequency also by optimizing the value of the currents supplied to the respective differential circuits.