Abstract: To provide a method of forming a resist pattern in a readily controllable manner and at low costs, in a first exposure step, a resist layer is subject to exposure through a mask. In the next, first developing step, a stepped portion 4 is formed in the resist layer. In a second exposure step, the resist layer is again subject to exposure. At this time, phase shift by 180.degree. occurs in the stepped portion so as to allow some area of the resist layer along the step to be not subject to exposure. In the second developing step, the exposed area of the resist layer 2 is removed to form a resist pattern along the step. Accordingly, the present invention is less subject to diffraction than the case where a phase shifter is employed, and is able to form a resist pattern in a readily controllable manner and reduce fabrication costs.

Abstract: To minimize error in size and form a thick oxide layer as field insulating means in a narrow isolation region, a method of fabricating a semiconductor device is carried out as followings.A polysilicon layer 3 is formed on a silicon substrate 1. A silicon nitride layer 5 is then formed on the polysilicon layer 3. Thereafter, an aperture 7 is formed in the silicon nitride layer 5 and reaches the polysilicon layer. A silicon layer 9 is formed in the aperture 7 by epitaxial growth technique. The silicon layer 9 is selectively oxidized to form an oxide layer 10 as field insulating means. The silicon nitride layer 5 and a portion of the polysilicon layer 3 which was left unoxidized are removed. This makes it possible to form the desired thick oxide layer as field insulating means in a narrow region.

Abstract: A writing circuit for non-volatile memory capable of preventing the structure of the circuit from becoming complicated in an integrated circuit from the points of view of logic and layout by reducing the number of kinds of control signal voltages. The circuit includes a first NMOS transistor N1, a first PMOS transistor P1, a second NMOS transistor N2 which serves as a non-volatile memory write terminal and a depression type MOS transistor D1 having a source to which a control signal PGM for controlling the output condition of the above-mentioned write terminal is applied.

Abstract: In a waveform data reproducing apparatus for a digital audio system, deterioration of sound quality is prevented by a digital audio waveform data reproducing apparatus which includes a digital preemphasis circuit 12 for digitally preemphasis-processing digital audio waveform data a1 to produce digitally preemphasized data c1, a D/A converter 14 for D/A-converting either the waveform data a1, or the digitally preemphasized data c1, a switch circuit 13 for causing the waveform data a1 to be connected to the D/A converter 14 when the waveform data a1 has been emphasis-processed, and for causing the digitally preemphasized waveform data c1 to be connected to the D/A converter 14 when the waveform data a1 is not emphasis-processed, and an analog deemphasis circuit 14 for analogically deemphasis-processing the output signal from the D/A converter 14.

Abstract: There is disclosed a voltage-controlled oscillator circuit capable of being operated at low power supply voltages and accomplishing low electric power consumption. The circuit permits the duty cycle to be controlled well. The circuit is capable of operating at high speeds. The circuit comprises a first and a second dynamic latch circuits producing oscillation output. Each dynamic latch circuit consists of a series combination of a P-channel MOS transistor and an N-channel MOS transistor. An output terminal is connected to the junction of these two transistors. The output from each latch circuit is inverted according to the voltage at the gate of each MOS transistor and dynamically latches the state of the output. This inversion is performed by turning on the MOS transistors by first and second capacitive elements and by first and second comparator circuits. The capacitive elements are charged and discharged by the outputs from the dynamic latch circuits.

Abstract: A method of accurately recording and reproducing an analog signal having a wide dynamic range with a small amount of information first samples amplitude values of an analog waveform which are then converted to a digital signal. Plural frames of data are stored in a buffer circuit. For each frame, the differences between successive values of the digital signal are extracted to form a second digital signal having an amount of shift S common to one frame, which is established and stored in a memory. In response to the amount of shift, the second digital signal is shifted toward lower bits thereof to compress the second digital signal into a third digital signal having less bits which is stored. When the difference values are small, the amount of shift is reduced to suppress errors produced during compression. When the difference values are large dynamic range is obtained, thereby coping with great signal variations without neglecting small variations in the analog signal.

Abstract: A downflow spin dryer, includes a housing; a rotor rotating within the housing in a direction of rotation, the rotor including first and second opposite mounting holes at different heights; a cradle fitted within the rotor for accommodating semiconductor substrates to be dried, the cradle having a rear portion and a front portion as viewed with respect to the direction of rotation of the rotor, the cradle being fitted to the rotor such that the rear portion of the cradle is at a lower position than the front portion of the cradle, the cradle including first and second opposite mounting holes in alignment with the first and second mounting holes, respectively, of the rotor when the cradle is fitted within the rotor, the first and second mounting holes of the cradle being at the same height; screws for entering the first mounting holes of the cradle and the rotor, and for entering the second mounting holes of the cradle and the rotor, so as to mount the cradle within the rotor; an air inlet in an upper surface

Abstract: A serial-to-parallel type multiplier capable of performing a highspeed calculation with high precision includes a selection circuit provided in a unit calculation block, an output of this selection circuit being input into an adder, and the selection circuit selectively outputs either a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within one unit time period or a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within a unit time period prior to the above-described one unit time period.

Abstract: To provide a resistor array circuit device and variable gain device which make possible precise setting of attenuation factors and the like as well as prevention of generation of gridge noise, a resistor array circuit device has resistors R1.sub.1 to R1.sub.n-1, each with a resistance value R, resistors R2.sub.1 to R2.sub.n, each with a resistance value aR, resistor R3 having a resistance value (l+b)R, switches SW.sub.1 to SW.sub.n for switching connection of resistors R2.sub.1 to R2.sub.n to a terminal T3 or a terminal T4, and a control circuit for controlling switches SW.sub.1 to SW.sub.n so that resistors R2.sub.1 to R2.sub.m-1 on a terminal T1 side of an arbitrary resistor R2.sub.m are connected to terminal T4 and resistors R2.sub.m to R2.sub.n on a terminal T2 side of resistor R2.sub.m are connected to terminal T3, the values of the a and b being determined based on b={-1+(1+4a).sup.1/2 }/2 and 1/2<a/(1+a+b).

Abstract: An integrated circuit device includes a first insulation layer formed on a substrate; a second insulation layer formed above the first insulation layer; a thin-film resistor formed on the second insulation layer; a third insulation layer in covering relation to the thin-film resistor and the second insulating layer; first contact holes penetrating the third insulation layer in association with the thin-film resistor; second contact holes penetrating through the second and third insulation layers; and conductive layers for electromagnetically shielding the thin-film resistor, the conductive layers including a first conductive layer formed between the first and second insulation layers below the thin-film resistor and a wiring layers formed above the thin-film resistor within the first and second contact holes.

Abstract: A sampling rate converter for converting a first signal having a first sampling rate to a second signal having a second sampling rate, includes a circuit for generating first data corresponding to the ratio of the second sampling rate to the first sampling rate. A second circuit generates second data by correcting the first data with corrective data. A third circuit generates third data corresponding to an estimated output timing of the second signal based upon the second data. A comparator compares the third data with a fourth data corresponding to the actual output timing of the second signal to generate comparative data. A corrective circuit is responsive to the comparative data to generate the corrective data. A further circuit is responsive to the first and third data for generating the second signal.

Abstract: A semiconductor device has a DRAM portion forming a cache memory and a flash memory portion fabricated on a common substrate, fabricated by a process based on the process of fabricating the flash memory portion. An electrode layer common to capacitors of the DRAM portion and a floating gate layer of the flash memory portion are formed simultaneously from the same material. An electrode layer of the upper capacitor of the DRAM portion, a gate electrode layer for a transistor of the DRAM portion, and a control gate layer of the flash memory portion are formed simultaneously from the same material.

Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.

Abstract: A method of making a semiconductor device having formed thereon an inductor comprises a silicon substrate. A cut out region is obtained by removing a part of the silicon substrate in a hollow shape which may be a hollow cavity or a hollow cavity with an insulating material having a low complex permittivity such as silicon oxide buried therein. An insulator layer is formed on the cut out region and on the periphery thereof. A connection layer serves as one of the leads of the inductor and is formed using an electric conductive material such as a metal or doped polycrystalline silicon. A contact hole is provided in the interlayer insulation layer. A connection layer serves as an inductor and the other lead of the inductor, which is formed using an electric conductive material such as a metal. A protective insulator layer is also provided on the top of the structure.