Abstract: In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory having a memory cell with two floating gates, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness.

Abstract: A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

Abstract: Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an O2 plus Cl2 plasma and/or bias power during the plasma etch is used as a tuning parameter.

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract: Methods for making memory devices are disclosed for forming germanium nanocrystals in an oxynitride layer. The method includes: forming a first dielectric layer over a substrate; forming an oxynitride layer containing germanium nanocrystals over the first dielectric layer; forming a second dielectric layer over the oxynitride layer; forming a gate over the second dielectric layer; and providing source, drain, and channel regions in the substrate. In one example, the channel region is positioned to correspond to at least a portion of the gate.

Abstract: A trench capacitor includes an electrode having a first conductive area formed in a trench provided in a substrate, and a second conductive area extending from a bottom of the trench, the second conductive area being electrically coupled to the first conductive area and spaced apart from the first conductive area; a storage node having a first conductive extension extending into a first dielectric space provided between the first conductive area and the second conductive area of the electrode, and a second conductive extension extending into a second dielectric space provided within the second conductive area of the electrode; and a dielectric layer electrically insulating the electrode from the storage node.

Abstract: A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall doping process is performed to form a doped region in the substrate at the upper trench sidewall. The blocking layer is removed from the trench. Because the blocking layer prevent dopants from reaching the bottom half of the trench during the sidewall doping process, junction leakage at the bottom section of the trench is prevented.

Abstract: A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor having a current path coupled between the output of the inverter an the output node, a first transistor circuit coupled between the first power supply node and the third power supply node having a first input coupled to the output of the inverter, a second input coupled to the output node, and an output, and a second transistor circuit coupled between the output node and the third power supply node having a first input coupled to the output of the first transistor circuit and a second input coupled to the input node.

Abstract: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The vertical transistor includes a first doped region, a second doped region, a gate and a gate insulating layer. The first doped region is located in the sidewall and is coupled with the capacitor. The second doped region is located in a top portion of the pillar. The gate is disposed on the sidewall of the pillar between the first and the second doped regions, and the gate insulating layer is disposed between the sidewall and the gate.

Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160).

Abstract: A sorting circuit (140) transfers data between a first group of at least four lines (134) on which the data items are arranged based on their addresses, and a second group of lines (138, WD0R, WD0F, WD1R, WD1F) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

Abstract: A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench.

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract: The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

Abstract: An operating method for a fault detection of a semiconductor process and a diagnostic system for fault detection in a semiconductor process are described. By using the method and the diagnostic system, the real-time process parameters collected during the process is performed by the tool become meaningful and are correlated with the historic process performance data obtained by the post process metrology process. Moreover, the method and the diagnostic system further provide an alarm index for the process performed on the tool to actually reflect the process environment during the process is performed after correlating the real-time process parameters and the historic process performance data. With referring to the alarm index, the current process performance under the real-time process parameters in the tool can be accurately diagnosed.