Patents Assigned to pSemi Corporation
  • Patent number: 10784861
    Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventor: Gary Chunshien Wu
  • Patent number: 10784818
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 10784855
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 10775827
    Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 15, 2020
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
  • Patent number: 10777636
    Abstract: High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: September 15, 2020
    Assignee: pSemi Corporation
    Inventor: Abhijeet Paul
  • Patent number: 10770770
    Abstract: A low loss, wide band, phase shifter utilizing one or more transformers in presented. In one case, the phase shifter includes a reflective SPDT switch that is coupled to a transformer. In another case, the phase shifter includes a distributed SPDT switch that includes switchable conduction paths having series connected unit elements of a same phase shift. The transformer may be part of an existing circuit and may be reused to provide the functionality of the phase shifter by introducing the reflective or the distributed SPDT switch.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventor: Vikas Sharma
  • Patent number: 10770974
    Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
  • Patent number: 10770480
    Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Simon Edward Willard, Alain Duvallet, Merlin Green, Sivakumar Kumarasamy
  • Patent number: 10768218
    Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Dan William Nobbe, Ronald Eugene Reedy, Peter Bacon, James S. Cable
  • Patent number: 10771059
    Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Eric S. Shapiro, Payman Shanjani
  • Patent number: 10770976
    Abstract: In a power converter, a regulator that receives a first voltage couples to a switched-capacitor converter that provides a second voltage. Slew-control circuitry controls slew rate within the switched-capacitor converter during operation thereof. A controller controls the operation of both the regulator and the switched-capacitor converter.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: David Giuliano, David Kunst
  • Patent number: 10771025
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10763257
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 1, 2020
    Assignee: pSemi Corporation
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Patent number: 10763798
    Abstract: An amplifier with switchable and tunable harmonic terminations and a variable impedance matching network is presented. The amplifier can adapt to different modes and different frequency bands of operation by appropriate switching and/or tuning of the harmonic terminations and/or the variable impedance matching network.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 1, 2020
    Assignee: pSemi Corporation
    Inventors: Gary Frederick Kaatz, Chris Olson
  • Patent number: 10756678
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 25, 2020
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
  • Patent number: 10756166
    Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ?MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ?MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 25, 2020
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
  • Patent number: 10756684
    Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 25, 2020
    Assignee: pSemi Corporation
    Inventors: Dan William Nobbe, David Halchin, Jeffrey A. Dykstra, Michael P. Gaynor, David Kovac, Kelly Michael Mekechuk, Gary Frederick Kaatz, Chris Olson
  • Patent number: 10734982
    Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 4, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Merlin Green
  • Patent number: 10734893
    Abstract: A power converter includes a charge pump in which transistors transition between conducting and non-conducting states thereby causing said pump capacitors to be interconnected in different arrangements at different times. Among the transistors is one that transitions into a conducting state when a source and gate of that transistor are at equal potentials.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: August 4, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Arezu Bagheri
  • Patent number: 10734892
    Abstract: A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 4, 2020
    Assignee: pSemi Corporation
    Inventor: Gregory Szczeszynski