Abstract: Electronic oscillator designs and methods that do not require an accurate voltage and current reference to be provided, and which output an accurate frequency waveform over a range of voltage supply and temperature variations. Embodiments of the present invention are particularly well-suited for IC designs with very limited layout area and a tight oscillator frequency spread requirement. An embodiment uses a current subtraction technique that provides an essentially constant through a bias generation circuit when the voltage of the voltage source exceeds a selected value. An embodiment includes a temperature-compensation circuit, coupled to the bias generation circuit, that includes at least one NFET and at least one negative temperature coefficient resistor and is configured to pass a temperature-compensated current through the at least one NFET.

Abstract: A compact RF switch with improved isolation is presented. According to one aspect, the RF switch includes a basic single-pole single-throw (SPST) switch element that includes an inductor in parallel with a series FET transistor. An inductance of the inductor is selected to provide in combination with an off capacitance of the series FET transistor a resonance at a specific frequency of interest. The frequency of interest can be in-band or out-of-band, including the band's fundamental frequency or a harmonic thereof. According to another aspect, the inductor is conditionally coupled to the series FET transistor via a reduced size FET transistor. Complex RF switches can include a plurality of the SPST switch elements, each tuned to a same or different frequency of interest. According to yet another aspect, SPST switch elements in their OFF states can provide matching to an SPST element in the ON state.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

Abstract: Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

Abstract: Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: Various methods and circuital arrangements for protection of a power amplifier (PA) from high input power conditions are presented. According to one aspect, a protection circuit coupled to a stage of the PA limits a current through the stage during the high input power conditions. Limiting of the current is provided by a current limiter circuit that includes a current generator coupled to a current mirror. The current is limited to a high value that is based on a reference current generated by the current generator. In one aspect, the reference current is programmable or variable. In another aspect the protection circuit includes a clamp that limits a low voltage at an output of the current limiter circuit. In another aspect, the protection circuit includes a pre-charge circuit that pre-charges the output of the current limiter circuit. In another aspect a filter is embedded within the current limiter circuit.

Abstract: Circuits and methods that can rapidly detect voltage degradation in a positive charge pump output and discharge control node accumulated charge (CNAC), thereby forcing the positive charge pump into a high-power mode. Embodiments include circuitry configured to provide a load current to a positive charge pump, including a low-dropout regulator (LDO) having a pass device that includes a control input, and a rapid charge transfer circuit coupled to the control input of the pass device and configured to be coupled to a source of a trigger voltage, the rapid charge transfer circuit configured to transfer a charge to or from the control input of the pass device when the trigger voltage falls sufficiently below a specified level so as to rapidly place the pass device in a higher conduction state, and to automatically cease to provide the transfer the charge after a settable amount of time.

Abstract: Methods and devices to control radiated spurious emission (RSE) in an RF antenna switch are presented. The RF antenna switch includes a through stack that includes at least one regular N-type FET transistor and a plurality of intrinsic N-type FET transistors, and a shunt stack that includes a plurality of intrinsic N-type FET transistors. During an inactive mode of operation, the regular transistor turns OFF to present a high impedance. The RF antenna switch includes a termination stack having a plurality of regular P-type FET transistors that are activated during the inactive mode to present a termination impedance to the antenna. A bias signal generator that remains partially active during the inactive mode of operation to generate positive and negative control voltages having magnitudes that are sufficiently high to maintain ON/OFF control of the transistors of the stacks.

Abstract: Frequency-selective feedback circuits and methods for an amplifier (particularly LNAs) that improve power supply rejection in feedback circuits, reduce non-linearities caused by low-frequency noise coupled to the input of the LNA, and improve settling times of the quiescent bias-point of the LNA. Some embodiments allow multiple modes of operation to allow selection of gain versus linearity characteristics. One aspect of the present invention includes an input matching feedback circuit configured to be coupled between an input terminal of an amplification core and a feedback node in the output signal path of the amplification core, the input matching feedback circuit including a power supply rejection resistor configured to provide a low-impedance path to a reference potential for low-frequency noise.

Abstract: Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of a switch to remove a decoupling capacitor from an RF circuit on an integrated circuit (IC) pin where the storage cap is connected; or modifying the turn-on threshold of an electrostatic discharge protection device (ESD) on the IC pin with the storage cap present to reduce susceptibility to turning on the ESD with the RF signal; or de-Qing the analog and digital core capacitances to minimize their contribution to resonance; or a combination thereof.

Abstract: Methods and devices for implementing vias as third-dimension connections in double-sided laminate packages for RF front-end circuits are disclosed. The described methods and devices are based on implementing components of an electronic module in two different integrated circuits and dispose the two integrated circuits on the opposite side of an isolating laminate. The components within one integrated circuit can be coupled to the components on the other integrated circuit by creating vias inside the laminate.

Abstract: Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of resonance-canceling inductors to counteract the capacitive reactance caused by parasitic capacitances and/or decoupling capacitors utilized in such systems. Solutions that incorporate series resistors to distribute the resonance across the frequency band of operation are also described. Additionally, devices that employ digitally tuned capacitors to shift the resonance frequency outside the operational band are presented.

Abstract: Circuits and methods that enable a charge pump to provide sufficient charge to the gate of a switch NFET to turn the NFET ON within a specified switching time requirement but with minimal generation of electronic noise. An embodiment includes a dual-oscillator circuit configured to output from a first oscillator a first frequency signal from a first oscillator during normal operation, and to output from a second oscillator a second frequency signal higher in frequency than the first frequency signal for a selected time determined by a counter. An embodiment includes a charge pump coupled to the dual-oscillator circuit and configured to output an electrical charge as a function of an applied frequency signal from the dual-oscillator circuit, wherein application of the second frequency signal output during counting increases the amount of electrical charge output by the charge pump.

Abstract: Methods and apparatuses for providing a reduction in output power of a balanced amplifier configuration are presented. According to one aspect, reduction of the output power is provided by deactivating one of the two amplification paths of the balanced amplifier. According to another aspect, impedances seen at ports of input and output couplers of the balanced amplifier configuration part of a deactivated amplification path are selectively switched in dependence of operation according to the reduced output power or according to normal output power. In addition, or in the alternative, impedance seen at an isolated/terminated port of the input and/or the output coupler is selectively switched in dependence of the operation. When operating according to the reduced output power, values of the switched impedances can be adjusted to tune a frequency response of the balanced amplifier.

Abstract: Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

Abstract: Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

Abstract: Briefly, example architectures and/or circuit topologies are disclosed herein that may be implemented, in whole or in part, to facilitate and/or support one or more operations and/or techniques for battery management infrastructure, such as for use with one or more power converters, which may include, for example, one or more switched-capacitor power converters.