Abstract: Methods and devices to control radiated spurious emission (RSE) in an RF antenna switch are presented. The RF antenna switch includes a through stack that includes at least one regular N-type FET transistor and a plurality of intrinsic N-type FET transistors, and a shunt stack that includes a plurality of intrinsic N-type FET transistors. During an inactive mode of operation, the regular transistor turns OFF to present a high impedance. The RF antenna switch includes a termination stack having a plurality of regular P-type FET transistors that are activated during the inactive mode to present a termination impedance to the antenna. A bias signal generator that remains partially active during the inactive mode of operation to generate positive and negative control voltages having magnitudes that are sufficiently high to maintain ON/OFF control of the transistors of the stacks.

Abstract: Frequency-selective feedback circuits and methods for an amplifier (particularly LNAs) that improve power supply rejection in feedback circuits, reduce non-linearities caused by low-frequency noise coupled to the input of the LNA, and improve settling times of the quiescent bias-point of the LNA. Some embodiments allow multiple modes of operation to allow selection of gain versus linearity characteristics. One aspect of the present invention includes an input matching feedback circuit configured to be coupled between an input terminal of an amplification core and a feedback node in the output signal path of the amplification core, the input matching feedback circuit including a power supply rejection resistor configured to provide a low-impedance path to a reference potential for low-frequency noise.

Abstract: Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of a switch to remove a decoupling capacitor from an RF circuit on an integrated circuit (IC) pin where the storage cap is connected; or modifying the turn-on threshold of an electrostatic discharge protection device (ESD) on the IC pin with the storage cap present to reduce susceptibility to turning on the ESD with the RF signal; or de-Qing the analog and digital core capacitances to minimize their contribution to resonance; or a combination thereof.

Abstract: Methods and devices for implementing vias as third-dimension connections in double-sided laminate packages for RF front-end circuits are disclosed. The described methods and devices are based on implementing components of an electronic module in two different integrated circuits and dispose the two integrated circuits on the opposite side of an isolating laminate. The components within one integrated circuit can be coupled to the components on the other integrated circuit by creating vias inside the laminate.

Abstract: Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of resonance-canceling inductors to counteract the capacitive reactance caused by parasitic capacitances and/or decoupling capacitors utilized in such systems. Solutions that incorporate series resistors to distribute the resonance across the frequency band of operation are also described. Additionally, devices that employ digitally tuned capacitors to shift the resonance frequency outside the operational band are presented.

Abstract: Circuits and methods that enable a charge pump to provide sufficient charge to the gate of a switch NFET to turn the NFET ON within a specified switching time requirement but with minimal generation of electronic noise. An embodiment includes a dual-oscillator circuit configured to output from a first oscillator a first frequency signal from a first oscillator during normal operation, and to output from a second oscillator a second frequency signal higher in frequency than the first frequency signal for a selected time determined by a counter. An embodiment includes a charge pump coupled to the dual-oscillator circuit and configured to output an electrical charge as a function of an applied frequency signal from the dual-oscillator circuit, wherein application of the second frequency signal output during counting increases the amount of electrical charge output by the charge pump.

Abstract: Methods and apparatuses for providing a reduction in output power of a balanced amplifier configuration are presented. According to one aspect, reduction of the output power is provided by deactivating one of the two amplification paths of the balanced amplifier. According to another aspect, impedances seen at ports of input and output couplers of the balanced amplifier configuration part of a deactivated amplification path are selectively switched in dependence of operation according to the reduced output power or according to normal output power. In addition, or in the alternative, impedance seen at an isolated/terminated port of the input and/or the output coupler is selectively switched in dependence of the operation. When operating according to the reduced output power, values of the switched impedances can be adjusted to tune a frequency response of the balanced amplifier.

Abstract: Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

Abstract: Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

Abstract: Briefly, example architectures and/or circuit topologies are disclosed herein that may be implemented, in whole or in part, to facilitate and/or support one or more operations and/or techniques for battery management infrastructure, such as for use with one or more power converters, which may include, for example, one or more switched-capacitor power converters.

Abstract: An apparatus for power conversion includes a transformation stage for transforming a first voltage into a second voltage. The transformation stage includes a switching network, a filter, and a controller. The filter is configured to connect the transformation stage to a regulator. The controller controls the switching network.

Abstract: Circuit and methods using a single low-noise amplifier (LNA) to provide amplification for a wide band of RF frequencies while maintaining high gain and a low noise factor. Embodiments include an amplifier circuit including an input signal path for receiving a wideband RF signal; a switched inductor tuning block coupled to the input signal path and configured to selectively couple one of a plurality of inductances to the input signal path; and an amplifier coupled to the switched inductor tuning block and configured to receive the RF signal after passage through the selected coupled inductance. The switched inductor tuning block includes a plurality of selectable branches, each including an RF input switch; an RF output switch; an inductor coupled between the RF input switch and the RF output switch; and first and second shunt switches coupled between a respective terminal of the inductor and circuit ground.

Abstract: Disclosed embodiments may include a power converter having a first and a second terminal, a charge pump power conversion circuit, and a protection circuit. The first terminal may be to receive an input voltage. The second terminal may be to output an output voltage. The charge pump power conversion circuit may be electrically coupled between the first terminal and the second terminal, and to convert the input voltage to the output voltage. The protection circuit may be electrically coupled to the charge pump power conversion circuit. The protection circuit may include a first switching device to, in response to a control signal, block a power flow from the first terminal to the second terminal, and from the second terminal to the first terminal.

Abstract: Fast-charge shaping circuits and methods for shaping the output of a fast-charge one-shot circuit so as to more precisely shape a fast-charge pulse to a bypass switch placed in parallel with an LNA bias resistor in order to decrease the response time of the LNA to circuit mode changes while minimizing perturbations. Accordingly, the settling time of the LNA during mode changes is less dependent on bias resistance, thereby enabling a Noise Figure improvement. A first approach staggers the release of a fast-charge pulse or pulses over multiple resistor segments to gradually increase the effective resistance of bias resistors. A second approach applies a diode and RC filter to a fast-charge pulse to shape the pulse to gradually increase the effective resistance of bias resistors. A third approach uses an op-amp and timing circuit to control the fast-charge pulse shape to gradually increase the effective resistance of bias resistors.

Abstract: Various methods and circuital arrangements for protection of a power amplifier from over temperature are presented. According to one aspect, a protection circuit coupled to a temperature sensor controls a biasing current or voltage to the power amplifier to limit a power dissipation through, and therefore a temperature of, the power amplifier when a high limit temperature is sensed. When the high limit temperature is sensed, the biasing current or voltage decreases as a linear function of the sensed temperature while allowing the power amplifier to operate. A slope of the linear function and a value of the high limit temperature can be made programmable. Programmability of the slope and the high limit temperature can be used to control biasing currents or voltages to a plurality of power amplifiers operating at different times and having different thermal requirements.

Abstract: Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Abstract: A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge. Determinations are made of effects of an uncontrolled accumulated charge and a controlled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the determinations, and the circuit is operated using techniques for ACC operatively coupled to the SOI MOSFET.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.