Patents Assigned to pSemi Corporation
  • Patent number: 12283876
    Abstract: Circuits and methods for sensing output current of a power converter, controlling output current in multiple parallel power converters, and enabling reconfigurability of output control for multiple parallel power converters. One embodiment includes a current sensing circuit configured to be coupled to a power converter, the current sensing circuit configured to receive a first voltage representative of an output current of the power converter and output a low-frequency filtered second voltage based on the first voltage and a high-frequency filtered third voltage based on the first voltage. In some embodiments, the first voltage is generated by sensing an output current of the power converter and converting the sensed output current to the first voltage. Other embodiments include a plurality of power stages and corresponding current sensing circuits, wherein the outputs of the low-frequency filters of the current sensing circuits are coupled in common.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 22, 2025
    Assignee: pSemi Corporation
    Inventors: Tim Wen Hui Yu, Gregory Szczeszynski
  • Patent number: 12278657
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: April 15, 2025
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 12255588
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: March 18, 2025
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
  • Patent number: 12242293
    Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: March 4, 2025
    Assignee: pSemi Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 12244242
    Abstract: An apparatus for conversion between AC and DC voltages includes a rectifier and first and second stages coupled to each other and having a regulator and a switched-capacitor circuit respectively. The first stage receives a first voltage from the rectifier and the second stage provides a second voltage. A controller controls the first and second stages.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: March 4, 2025
    Assignee: pSemi Corporation
    Inventors: David M. Giuliano, David Kunst
  • Patent number: 12237327
    Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: February 25, 2025
    Assignee: pSemi Corporation
    Inventors: Shashi Samal, Matt Allison
  • Patent number: 12237821
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: February 25, 2025
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Patent number: 12237765
    Abstract: In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: pSemi Corporation
    Inventor: David Giuliano
  • Patent number: 12231114
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: February 18, 2025
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 12230592
    Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: February 18, 2025
    Assignee: pSemi Corporation
    Inventors: William R. Smith, Jr., Jaroslaw Adamski, Dan William Nobbe, Edward Nicholas Comfoltey, Jingbo Wang
  • Patent number: 12231087
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 18, 2025
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 12218586
    Abstract: An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. The power converter has switch elements configured to electrically interconnect capacitors to one another and/or to the first or second voltage in successive states. The switch elements are configured to interconnect at least some capacitors to one another through the switch elements. A controller causes the reconfigurable switched capacitor power converter to transition between first and second operation modes. The controller minimizes electrical transients arising from transition between modes. In the first operating mode, the power converter operates with a first conversion gain. In the second operating mode, it operates with a second conversion gain.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: February 4, 2025
    Assignee: pSemi Corporation
    Inventors: Aichen Low, David M. Giuliano, Gregory Szczeszynski, Jeff Summit, Oscar Blyde
  • Patent number: 12218575
    Abstract: In a power converter having a regulator and charge pump, both of which operate in plural modes, a controller receives information indicative of the power converter's operation and, based at least in part on said information, causes transitions between regulator modes and transitions between charge-pump modes.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: February 4, 2025
    Assignee: pSemi Corporation
    Inventors: Aichen Low, Gregory Szczeszynski, David M. Giuliano
  • Patent number: 12218637
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: February 4, 2025
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 12212231
    Abstract: A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 28, 2025
    Assignee: pSemi Corporation
    Inventor: David Giuliano
  • Patent number: 12212232
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: January 28, 2025
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 12212291
    Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: January 28, 2025
    Assignee: pSemi Corporation
    Inventors: Miles Sanner, Emre Ayranci
  • Patent number: 12206395
    Abstract: Multi-way signal switch designs and methods for reducing parasitic capacitance. In a first embodiment, two or more series-coupled FET shunt-switches are coupled to at least one switch cell through-switch. At least one shunt-switch is set to an OFF state during normal operation so as to function as a capacitor, while at least one other shunt-switch is set to behave like a capacitor in a switch cell ON state, and is set to behave like a resistor in a switch cell OFF state. In a second embodiment, the combination of at least one FET shunt-switch coupled in series with a capacitor functions as a shunt connection for the signal path, wherein the FET shunt-switch is set to behave like a capacitor when the switch cell is in an ON state, and is set to behave like a resistor when the switch cell is in an OFF state.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 21, 2025
    Assignee: pSemi Corporation
    Inventors: Yucheng Tong, Parvez H. Daruwalla
  • Patent number: 12205954
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: January 21, 2025
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Patent number: 12191833
    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 7, 2025
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk