Abstract: Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.

Abstract: In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.

Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.

Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: Methods and systems for determining the error vector magnitudes for an RF device by fitting voltage magnitudes to a Rayleigh distribution to produce weighting parameters for an EVM calculation, either in simulation for designing the RF device or as validation measurements from a physical RF device.

Abstract: In a power converter having a regulator and charge pump, both of which operate in plural modes, a controller receives information indicative of the power converter's operation and, based at least in part on said information, causes transitions between regulator modes and transitions between charge-pump modes.

Abstract: An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. The power converter has switch elements configured to electrically interconnect capacitors to one another and/or to the first or second voltage in successive states. The switch elements are configured to interconnect at least some capacitors to one another through the switch elements. A controller causes the reconfigurable switched capacitor power converter to transition between first and second operation modes. The controller minimizes electrical transients arising from transition between modes. In the first operating mode, the power converter operates with a first conversion gain. In the second operating mode, it operates with a second conversion gain.

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.

Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

Abstract: Multi-way signal switch designs and methods for reducing parasitic capacitance. In a first embodiment, two or more series-coupled FET shunt-switches are coupled to at least one switch cell through-switch. At least one shunt-switch is set to an OFF state during normal operation so as to function as a capacitor, while at least one other shunt-switch is set to behave like a capacitor in a switch cell ON state, and is set to behave like a resistor in a switch cell OFF state. In a second embodiment, the combination of at least one FET shunt-switch coupled in series with a capacitor functions as a shunt connection for the signal path, wherein the FET shunt-switch is set to behave like a capacitor when the switch cell is in an ON state, and is set to behave like a resistor when the switch cell is in an OFF state.

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.

Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.