Abstract: In a power converter having a regulator and charge pump, both of which operate in plural modes, a controller receives information indicative of the power converter's operation and, based at least in part on said information, causes transitions between regulator modes and transitions between charge-pump modes.

Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

Abstract: A cascade multiplier includes a switch network having switching elements, a phase pump, and a network of pump capacitors coupled with the phase pump and to the switch network. The network of pump capacitors includes first and second capacitors, both of which have one terminal DC coupled with the phase pump, and a third capacitor coupled with the phase pump through the first capacitor.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: Multi-way signal switch designs and methods for reducing parasitic capacitance. In a first embodiment, two or more series-coupled FET shunt-switches are coupled to at least one switch cell through-switch. At least one shunt-switch is set to an OFF state during normal operation so as to function as a capacitor, while at least one other shunt-switch is set to behave like a capacitor in a switch cell ON state, and is set to behave like a resistor in a switch cell OFF state. In a second embodiment, the combination of at least one FET shunt-switch coupled in series with a capacitor functions as a shunt connection for the signal path, wherein the FET shunt-switch is set to behave like a capacitor when the switch cell is in an ON state, and is set to behave like a resistor when the switch cell is in an OFF state.

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.

Abstract: Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

Abstract: Circuits and methods for achieving good amplifier AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance. Embodiments compensate for a non-linear distortion profile (e.g., an AM-PM and/or AM-AM profile) in an amplifier by pre-processing an input signal, such as a radio-frequency signal, to alter the non-linear distortion profile of the input signal so as to compensate for the non-linear distortion profile imposed by a coupled device, such as an amplifier.

Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.

Abstract: An apparatus for power conversion comprises a voltage transformation element, a regulating element, and a controller; wherein, a period of the voltage transformation element is equal to a product of a coefficient and a period of the regulating circuit, and wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of said integer.

Abstract: Methods and devices for reducing coupling of RF frequency components between different bands of an RF system are presented. According to one aspect, a notch filter having a notch centered at a harmonic of a fundamental frequency of a first band transmit side is coupled to an output of an LNA of the first band. According to another aspect, the harmonic is a second harmonic, a third harmonic or higher order harmonics. According to another aspect, the notch filter includes a plurality of notches at respective plurality of harmonics. According to a further aspect, the notch has an attenuation of 30 dB or greater at the second harmonic and 10 dB or greater at the third harmonic. Further included is a method for reducing coupling of harmonics of signals transmitted in the first band into a receive path of the second band, thereby increasing noise figure/sensitivity performances of the receive path.

Abstract: Disclosed embodiments may include a power converter system with fault handling. Embodiments may include first and second power converters each including an output terminal and a control terminal, the first and second power converters to regulate voltage or current at their respective output terminals based on a voltage at their respective control terminals, the output terminals coupled to each other, and the control terminals coupled to each other; wherein the first power converter comprises: a circuit to detect a fault condition associated with the first power converter and to generate a first fault signal at the control terminal of the first power converter after the detecting the fault condition associated with the first power converter; wherein the second power converter comprises: a circuit to change an operating mode of the second power converter after generating the first fault signal at the control terminal of the first power converter.

Abstract: Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

Abstract: Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

Abstract: This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.