Patents Assigned to pSemi Corporation
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Patent number: 11764669Abstract: Subject matter disclosed herein may relate to power converters, and may more particularly relate to multi-stage hybrid power converters, for example.Type: GrantFiled: December 22, 2020Date of Patent: September 19, 2023Assignees: The Trustees of Princeton University, pSemi CorporationInventors: Minjie Chen, Yenan Chen, David Giuliano
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Publication number: 20230283176Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.Type: ApplicationFiled: December 9, 2022Publication date: September 7, 2023Applicant: pSemi CorporationInventors: David GIULIANO, Gregory SZCZESZYNSKI, Raymond BARRETT, JR.
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Patent number: 11742847Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.Type: GrantFiled: August 9, 2022Date of Patent: August 29, 2023Assignee: pSemi CorporationInventors: Ethan Prevost, Michael Conry
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Patent number: 11742820Abstract: A phase shifter unit cell or a connected set of such cells that can be well isolated from external circuitry and which do not introduce insertion loss into an RF signal path, exhibit good return loss, and further provides additional advantages when combined with bracketing attenuator circuits. More particularly, embodiments integrate a high-isolation function within a phase shifter circuit by breaking the complimentary nature of the control signals to a phase shifter cell to provide greater control of switch states internal to the phase shifter cell and thus enable a distinct high-isolation state, and by including a switchable shunt termination resistor for use in the high-isolation state. Some embodiments are serially coupled to attenuator circuits to enable synergistic interaction that reduces overall die size and/or increases isolation. One such embodiment positions a high-isolation phase shifter cell in accordance with the present invention between bracketing programmable attenuators.Type: GrantFiled: July 21, 2021Date of Patent: August 29, 2023Assignee: pSemi CorporationInventors: Eric S. Shapiro, Peter Bacon
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Patent number: 11742802Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.Type: GrantFiled: November 19, 2021Date of Patent: August 29, 2023Assignee: pSemi CorporationInventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
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Patent number: 11742848Abstract: Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.Type: GrantFiled: February 16, 2022Date of Patent: August 29, 2023Assignee: pSemi CorporationInventors: Buddhika Abesingha, Gregory Szczeszynski
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Patent number: 11735589Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.Type: GrantFiled: July 6, 2022Date of Patent: August 22, 2023Assignee: pSemi CorporationInventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
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Patent number: 11736102Abstract: A compact RF switch with improved isolation is presented. According to one aspect, the RF switch includes a basic single-pole single-throw (SPST) switch element that includes an inductor in parallel with a series FET transistor. An inductance of the inductor is selected to provide in combination with an off capacitance of the series FET transistor a resonance at a specific frequency of interest. The frequency of interest can be in-band or out-of-band, including the band's fundamental frequency or a harmonic thereof. According to another aspect, the inductor is conditionally coupled to the series FET transistor via a reduced size FET transistor. Complex RF switches can include a plurality of the SPST switch elements, each tuned to a same or different frequency of interest. According to yet another aspect, SPST switch elements in their OFF states can provide matching to an SPST element in the ON state.Type: GrantFiled: January 18, 2022Date of Patent: August 22, 2023Assignee: PSEMI CORPORATIONInventor: Michael P. Gaynor
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Patent number: 11728837Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.Type: GrantFiled: July 2, 2021Date of Patent: August 15, 2023Assignee: pSemi CorporationInventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
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Patent number: 11722162Abstract: Fail-safe methods and devices to protect the receiver of a transceiver in the event of an antenna failure are disclosed. The described devices implement inductive and capacitive elements to replace switches and can be used in any communication system or electronic circuit where the protection of a portion of the device from higher power signals is required. The inductive elements can be implemented using already existing inductors that are constituents of the receiver matching network. Configurations with off-chip capacitive or inductive components are also possible.Type: GrantFiled: February 2, 2022Date of Patent: August 8, 2023Assignee: PSEMI CORPORATIONInventors: Chengkai Luo, Payman Shanjani, Ravindranath D. Shrivastava
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Patent number: 11722114Abstract: An interdigitated RF filter. The interdigitated RF filter includes input fingers connected to an input node and output fingers connected to an output node where at least one input finger is connected the output node or at least one output finger is connected to the input node. The described interdigitated RF filter can be implemented in various configurations such as series, shunt, ladder or a combination thereof.Type: GrantFiled: April 18, 2022Date of Patent: August 8, 2023Assignee: PSEMI CORPORATIONInventor: Michael P. Gaynor
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Patent number: 11720136Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.Type: GrantFiled: November 15, 2022Date of Patent: August 8, 2023Assignee: pSemi CorporationInventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
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Patent number: 11716067Abstract: Circuits and methods that provide wider bandwidth and smaller IM inductances for phase change material (PCM) based RF switch networks. The present invention recognizes that it is beneficial to consider the total high parasitic capacitance to ground of the various PCM switches in an RF switch network as constituting two or more separate capacitive contributions. This leads to several “split capacitance” concepts, including signal-path splitting, switch-block splitting, stacked-switch splitting, and splitting parasitic capacitances due to layout discontinuities, in which compensating impedance matching inductances are inserted between additive capacitances.Type: GrantFiled: September 23, 2021Date of Patent: August 1, 2023Assignee: pSemi CorporationInventor: Jean-Luc Erb
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Patent number: 11711068Abstract: A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.Type: GrantFiled: November 10, 2020Date of Patent: July 25, 2023Assignee: pSemi CorporationInventors: John Birkbeck, Vikas Sharma, Kashish Pal, Mark James O'Leary
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Patent number: 11705873Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.Type: GrantFiled: October 13, 2022Date of Patent: July 18, 2023Assignee: pSemi CorporationInventors: Miles Sanner, Emre Ayranci
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Patent number: 11695407Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.Type: GrantFiled: December 6, 2021Date of Patent: July 4, 2023Assignee: pSemi CorporationInventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle
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Patent number: 11689161Abstract: Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.Type: GrantFiled: September 27, 2021Date of Patent: June 27, 2023Assignee: PSEMI CORPORATIONInventor: John Birkbeck
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Patent number: 11689101Abstract: Circuits and methods for adding a Current Mode signal into a Voltage Mode controller for fixed-frequency DC-to-DC power converters. A current-controlled voltage source (CCVS) generates a voltage proportional to the power converter output current, which voltage is combined with a comparison signal generated by comparing a target output voltage to the actual output voltage. The modified comparison signal generates a pulse-width modulation control signal that regulates the power converter output as a function of output voltage and some portion of output current. With the addition of an inductor current signal into the controller Voltage Mode feedback loop, the double pole predominant in constant conduction mode (CCM) mode can be smoothed over to improve stability, while discontinuous conduction mode (DCM) loop response is largely unchanged with or without the added Current Mode signal. Embodiments enable simplified compensation while covering a wider operating range.Type: GrantFiled: November 12, 2020Date of Patent: June 27, 2023Assignee: pSemi CorporationInventors: Brian Zanchi, Tim Wen Hui Yu, Gregory Szczeszynski
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Patent number: 11671135Abstract: An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.Type: GrantFiled: October 1, 2021Date of Patent: June 6, 2023Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Fleming Lam, Payman Shanjani
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Patent number: 11671091Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.Type: GrantFiled: July 28, 2021Date of Patent: June 6, 2023Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk