Abstract: In a power converter, a regulator that receives a first voltage couples to a switched-capacitor converter that provides a second voltage. Slew-control circuitry controls slew rate within the switched-capacitor converter during operation thereof. A controller controls the operation of both the regulator and the switched-capacitor converter.

Abstract: A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.

Abstract: Methods and devices for processing of RF signals according to different gain modes are presented. According to one aspect, an active amplification mode is provided by switchable active paths coupled to respective input RF signals and a passive attenuation mode is provided by switchable passive paths coupled to the respective RF signals. According to another aspect, a common switchable feedback path coupled to the switchable active paths is used to provide an active attenuation mode. Coupling of the common switchable feedback path to the switchable active path is provided by switches of the switchable passive paths, including for coupling both ends of the common switchable feedback path or just one end.

Abstract: A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

Abstract: Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.

Abstract: Methods and apparatuses for protecting a low voltage (LV) circuit implemented with LV transistors are presented. Protection is provided via a protection circuit operating in a high voltage domain defined by a varying supply voltage and a reference ground. The protection circuit generates high side, VH, and low side, VL, voltages to the LV circuit, while protecting the LV circuits from high voltage and maintaining a minimum difference voltage, VH?VL. The protection circuit generates the difference voltage based on a voltage across a resistor of a resistor ladder that is coupled between the varying supply voltage and the reference ground. The protection circuit includes a clamp circuit that limits the minimum difference voltage for low values of the supply voltage.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.

Abstract: Methods and devices for limiting the power level of low noise amplifiers (LNA) implemented in radio frequency (RF) receiver front-ends. The described methods are applicable to bypass, low and high gain modes of the LNA. According to the described methods, the decoder allows the signal to be clamped before or after being attenuated. The benefit of such methods is to improve large signal performances (e.g. IIP3, P1dB) of the RF receiver front-end, while still meeting the clamping requirements, or improve (lower) clamped output power, while still meeting large signal performances (e.g. IIP3, P1dB).

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.

Abstract: A single integrated circuit DC-to-DC conversion solution that can be used in conjunction with product designs requiring at least two different DC-to-DC conversion ratios, and in particular both divide-by-2 and divide-by-3 DC-to-DC buck conversion ratios or both multiply-by-2 and multiply-by-3 DC-to-DC boost conversion ratios. Embodiments are reconfigurable between a first Dickson converter configuration that includes at least two non-parallel capacitors (any of which may be off-chip) and associated controlled multi-phase switching to achieve a first conversion ratio, and a second Dickson converter configuration that includes a lesser equivalent number of capacitors than the first circuit configuration (which may be accomplished by parallelizing at least two non-parallel capacitors of the first configuration) and associated controlled multi-phase switching to achieve a second conversion ratio different from the first conversion ratio.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.

Abstract: Circuits and methods for providing at least a startup voltage for reversed-operation unidirectional power converters or bi-modal power converters sufficient to power at least an auxiliary circuit of such power converters while the normal supply voltage to at least the auxiliary circuit is insufficient to enable operation of the auxiliary circuit. Embodiments of the invention utilize an initial startup charge pump circuit to create a suitable startup voltage while the normal supply voltage to the auxiliary circuit is less than a specified voltage VMIN. Embodiments of the present invention also provide additional benefits, including small size since the initial startup charge pump circuit omits the use of an inductor, and high efficiency since the initial startup charge pump circuit may be disabled when the normal supply voltage to the auxiliary circuit is equal to or greater than VMIN.

Abstract: A controller controls a circuit that provides a variable current to a load and provides a constant voltage to the load. The controller controls switches to adaptively respond to a change in a load current by transitioning into or out of pulse-skipping mode.

Abstract: Methods and devices addressing power tracking of transmission systems using antenna arrays are disclosed. The disclosed teachings may be implemented on a channel element to channel element basis, are adaptive and can be implemented on short time durations such as time slots. Power efficiency can be improved when applying the described methods to the design of systems with antenna arrays.

Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.