Abstract: A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

Abstract: A switching network includes a switch, a driver for the switch, and a floating-regulator that powers the driver. The floating-regulator includes a shunt that is used only when testing the network. The shunt diverts biasing current so that it does not interfere with a measurement of an electrical property of a switch.

Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Abstract: An apparatus for conversion between AC and DC voltages includes a rectifier and first and second stages coupled to each other and having a regulator and a switched-capacitor circuit respectively. The first stage receives a first voltage from the rectifier and the second stage provides a second voltage. A controller controls the first and second stages.

Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

Abstract: Various methods and circuital arrangements for protection of an RF amplifier are presented. According to one aspect, the RF amplifier is part of switchable RF paths that may include at least one path with one or more attenuators or switches that can be used during normal operation to define different modes of operation of the at least one path. An RF level detector monitors a level of an RF signal during operation of any one of the switchable RF paths and may control the attenuators or switches to provide an attenuation of the RF signal according to a desired level of protection at an input and/or output of the RF amplifier. According to another aspect, the RF level detector may control a switch to force the RF signal through a different switchable RF path.

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.

Abstract: An apparatus for electric power conversion includes a converter having a regulating circuit and switching network. The regulating circuit has magnetic storage elements, and switches connected to the magnetic storage elements and controllable to switch between switching configurations. The regulating circuit maintains an average DC current through a magnetic storage element. The switching network includes charge storage elements connected to switches that are controllable to switch between plural switch configurations. In one configuration, the switches forms an arrangement of charge storage elements in which at least one charge storage element is charged using the magnetic storage element through the network input or output port. In another, the switches form an arrangement of charge storage elements in which an element discharges using the magnetic storage element through one of the input port and output port of the switching network.

Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Abstract: An apparatus for processing electric power includes a power-converter having a path for power flow between first and second power-converter terminals. During operation the first and second power-converter terminals are maintained at respective first and second voltages. Two regulating-circuits and a switching network are disposed on the path. The first regulating-circuit includes a magnetic-storage element and a first-regulating-circuit terminal. The second regulating-circuit includes a second-regulating-circuit terminal. The first-regulating-circuit terminal is connected to the first switching-network-terminal and the second-regulating-circuit terminal is connected to the second switching-network-terminal. The switching network is transitions between a first switch-configuration and a second switch-configuration. In the first switch-configuration, charge accumulates in the first charge-storage-element at a first rate.

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOD metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

Abstract: A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Various embodiments of energy storage elements for use in power converters are described. In one example embodiment, briefly, an integrated circuit (IC) for use with a power converter may comprise a first layer comprising a first set of devices disposed on a device face thereof; a second layer comprising a second set of devices disposed on a device face thereof; a first interconnect structure to be disposed between the first layer and an electrical interface, the first interconnect structure to electrically couple the first set of devices to one or more thru vias; and a second interconnect structure to be disposed between the first layer and the second layer, the second interconnect structure to electrically couple the second set of devices to the one or more thru vias. Likewise, in some instances, one or more thru vias may extend through at least one of the following: the first layer; the second layer; or any combination thereof.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.