Abstract: A method for training a super-resolution model, a super-resolution method, and a system are provided, and the super-resolution method and the system are implemented through an AI super-resolution model that is trained by the method. In the method, an input image is provided, and a magnification ratio and an image quality threshold are set. Pixel values of the input image are retrieved, and image features of the input image are extracted. Multiple channel images are obtained through a super-resolution model based on the image features and the magnification ratio. Phase information can be obtained according to the magnification ratio and positions of output pixels, and the phase information is used to obtain masks mapping to the channel images. Therefore, an output image can be reshuffled. After a comparison with the image quality threshold, model parameters of the output image can be assessed for training the AI super-resolution model.

Abstract: A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

Abstract: A crystal oscillator having a PMOS, an NMOS transistor, a feedback capacitor positioned between the source node and one of the first gate node and the second gate node; a shunt capacitor positioned between the source node and one of the power supply node and the ground node, an AC coupling capacitor positioned between the first gate node and the second gate node, and a crystal positioned between one of the first gate node and the second gate node and one of the ground node and the power supply node. A first DC coupling network couples a first bias node to the first gate node according to a state of a first gate voltage at the first gate node, and a second DC coupling network couples a second bias node to the second gate node according to a state of a second gate voltage at the second gate node.

Abstract: An image encoding method, comprising: (a) storing first frame data of a first frame to a first region of the first storage region; (b) reading the first frame data, and using frame data stored in the second storage region as first reference frame data to encode the first frame data to generate first reconstruction data of a first reconstruction frame; (c) before the first frame data is completely read from the first region, writing the first reconstruction data to a second region of the first storage region; and (d) deleting the frame data in the second storage region, writing second frame data of a second frame to a first region of the second storage region, encoding the second frame data using the first reconstruction data as second reference data to generate second reconstruction data, and then writing the second reconstruction data to a second region of the second storage region.

Abstract: A compensating circuit includes a matching circuit, for matching an initial signal and a transformed signal to generate a matched signal; a calculating circuit, coupled to the matching circuit, for calculating a function of the matched signal; a phase-rotating circuit, coupled to the calculating circuit, for rotating a phase of the function according to a determined phase to generate a phase-rotated function; a determining circuit, coupled to the phase-rotating circuit, for determining a parameter according to the phase-rotated function; and a mixing circuit, coupled to the determining circuit, for mixing the parameter and the transformed signal to generate a compensated signal.

Abstract: A method and apparatus for enhancing precision time protocol (PTP) timestamp precision using a machine learning (ML) circuit with aid of feature-and-model pre-selection (FMPS) and parameter pre-tuning (PPT) are provided. The apparatus includes a communication circuit, for performing communication operations for an electronic device, and the ML circuit, for performing time calculation for the communication circuit. The communication circuit includes a PTP timestamp generation circuit, for generating at least one timestamp in at least one packet; and the ML circuit includes a pre-selected model running on the ML circuit, the pre-selected model arranged to obtain a set of pre-selected features from the communication circuit, and convert the set of pre-selected features into at least one time calculation result according to a set of pre-tuned parameters, to allow the PTP timestamp generation circuit to generate the at least one timestamp according to the at least one time calculation result.

Abstract: The present invention provides a signal processing method, wherein the signal processing method includes the steps of: receiving a MST packet that complies with a DP specification; converting the MST packet into multiple SST packets; determining a number of valid data symbols in a transfer unit included in the multiple SST packets based on information of a horizontal blanking interval indicated by the MST packet or the multiple SST packets; and transmitting the multiple SST packets to a back-end device.

Abstract: A method used in controller circuit includes: using register circuit to store setting signal sent from CPU; using remapping index configuration register to store remapping index configuration value; referring to the setting signal to perform multiple consecutive direct memory access operations to access system memory; and, referring to at least one setting data in the setting signal to perform at least one specific direct memory access operation to access the system memory, to update the remapping index configuration value stored by the remapping index configuration register so as to perform a remapping index setting operation.

Abstract: The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.

Abstract: A speech synthesis system includes multiple modules/models. A vocal voice channel isolation module performs an isolation operation upon an audio input signal to generate multiple vocal voice channels and a single non-vocal voice channel. An automatic speech recognition (ASR) module selects a target vocal voice channel from the multiple vocal voice channels according to a source language text. A speech emotional recognition model performs a prediction operation upon each of the multiple vocal voice channels in order to generate a prediction result indicating a corresponding emotional classification. A feature adaptive text-to-speech (TTS) system performs a speech synthesis operation according to the source language text, a target language text, the target vocal voice channel, and the emotional classification, to generate a synthetic vocal voice.

Abstract: The present invention provides a circuitry including a clock buffer, a first circuit module, and a second circuit module. The clock buffer is configured to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider configured to divide the first clock signal to generate a plurality of first divided clock signals. The second circuit module includes a second frequency divider configured to divide the first clock signal to generate a plurality of second divided clock signals. During the frequency division operation, both the first circuit module and the second circuit module utilize the second clock signal for phase alignment, thereby ensuring that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.

Abstract: A display device for adjusting a streaming video includes a first display circuit configured with a first panel rate (PR); a detecting circuit, for detecting the first PR and a video frame rate (VFR) of the streaming video; a determination circuit, for determining a first frame number according to the VFR and the first PR in response to the VFR not being divisible by the first PR and the first PR not being divisible by the VFR; a computing circuit, for computing first motion vectors (MVs) of first frames in first group of pictures (GOPs) of the streaming video, and for selecting at least one first frame from the first frames according to the first MVs and the first frame number; and a processing circuit, for repeating or ignoring the at least one first frame in the first GOPs to generate second GOPs.

Abstract: The present invention provides an integrator used in a sigma-delta analog-to-digital converter, which includes a sampling circuit and an integrating circuit. By designing a specific switch with a charge averaging function in the sampling circuit, the voltage level of terminals of the multiple sampling capacitors can be averaged to be close to a voltage level of the input signal to be sampled before a sampling stage, so that the input buffer only requires lower drive capability to charge or discharge the sampling capacitor. Thus the power consumption of the input buffer can be reduced.

Abstract: A multiple-audio-source adaptive switching device and a method thereof are provided. The method includes: receiving the audio signal; extracting a plurality of sampling points from the audio signal, where one of the sampling points is defined as the first sampling point, and the rest of the sampling points are defined as a plurality of second sampling points; in response to that an absolute difference between each of the second sampling points and the first sampling point is determined to be greater than the first threshold value, accumulating the effective value to obtain an accumulated value; and in response to that the accumulated value is determined to be greater than the second threshold value, outputting the audio signal.

Abstract: A context management method of an edge artificial intelligence system includes: receiving a user question, appending an auxiliary information thereto to generate a current question, and storing it in a conversation history record using a mixer module; receiving the conversation history record, using a small LLM to classify the conversation history record into topic categories, and determining a topic category among the at least one topic category to which the current question belongs using a classifier module; and sorting history questions and history responses within the topic category to which the current question belongs in accordance with a similarity between the history questions and the current question and a similarity between the history responses and the current question to generate a prompt output sequence for the topic category to which the current question belongs and sending the prompt output sequence to an external LLM using a sorter module.

Abstract: A filter circuit and adjustable inductor thereof is related to a filter circuit including a power terminal, an output terminal, a power wiring, and an adjustable inductor. The power terminal is configured to receive an operation power. The output terminal is configured to output the operation power. The power wiring is coupled between the power terminal and the output terminal. The adjustable inductor is electrically connected between the power wiring and a ground terminal, and the adjustable inductor is configured to eliminate noise on the power wiring. The adjustable inductor includes a first transductor and a second transductor. The first transductor and the second transductor have inverted transconductance phases, and the second transductor is electrically connected between two ends of the first transductor.

Abstract: A method for correcting local-dimming parameters through global backlight adjustment and a circuit system are provided. The circuit system connects with a backlight control circuit of a display. In the method operated in the circuit system, when an image is received, the pixel values of each of the regions divided from the image can be counted so as to obtain a local maximum and a local average of every region, and a global average of the image. The region having a dark-field halo can be detected based on a local difference between the local maximum and the local average. A leakage level can be obtained by determining an impact of the dark-field halo on the whole image based on a threshold. The leakage level and the global average are referred to for calculating a gain for global backlight adjustment after performing local dimming.

Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.

Abstract: A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.

Abstract: An LC (inductor-capacitor) oscillator includes a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein: the source of the first NMOS transistor is shorted to the source of the first PMOS transistor; the source of the second NMOS transistor is shorted to the source of the second PMOS transistor; the first NMOS transistor and the second NMOS transistor are cross coupled via a first gate inductor and a first drain inductor; the first and second PMOS transistors are cross coupled via a second gate inductor and a second drain inductor; the first NMOS transistor and the first PMOS transistor are coupled via a first gate capacitor and a first drain capacitor; and the second NMOS transistor and the second PMOS transistor are coupled via a second gate capacitor and a second drain capacitor.