Abstract: A multiple-audio-source adaptive switching device and a method thereof are provided. The method includes: receiving the audio signal; extracting a plurality of sampling points from the audio signal, where one of the sampling points is defined as the first sampling point, and the rest of the sampling points are defined as a plurality of second sampling points; in response to that an absolute difference between each of the second sampling points and the first sampling point is determined to be greater than the first threshold value, accumulating the effective value to obtain an accumulated value; and in response to that the accumulated value is determined to be greater than the second threshold value, outputting the audio signal.

Abstract: The present invention provides an integrator used in a sigma-delta analog-to-digital converter, which includes a sampling circuit and an integrating circuit. By designing a specific switch with a charge averaging function in the sampling circuit, the voltage level of terminals of the multiple sampling capacitors can be averaged to be close to a voltage level of the input signal to be sampled before a sampling stage, so that the input buffer only requires lower drive capability to charge or discharge the sampling capacitor. Thus the power consumption of the input buffer can be reduced.

Abstract: A context management method of an edge artificial intelligence system includes: receiving a user question, appending an auxiliary information thereto to generate a current question, and storing it in a conversation history record using a mixer module; receiving the conversation history record, using a small LLM to classify the conversation history record into topic categories, and determining a topic category among the at least one topic category to which the current question belongs using a classifier module; and sorting history questions and history responses within the topic category to which the current question belongs in accordance with a similarity between the history questions and the current question and a similarity between the history responses and the current question to generate a prompt output sequence for the topic category to which the current question belongs and sending the prompt output sequence to an external LLM using a sorter module.

Abstract: A filter circuit and adjustable inductor thereof is related to a filter circuit including a power terminal, an output terminal, a power wiring, and an adjustable inductor. The power terminal is configured to receive an operation power. The output terminal is configured to output the operation power. The power wiring is coupled between the power terminal and the output terminal. The adjustable inductor is electrically connected between the power wiring and a ground terminal, and the adjustable inductor is configured to eliminate noise on the power wiring. The adjustable inductor includes a first transductor and a second transductor. The first transductor and the second transductor have inverted transconductance phases, and the second transductor is electrically connected between two ends of the first transductor.

Abstract: A method for correcting local-dimming parameters through global backlight adjustment and a circuit system are provided. The circuit system connects with a backlight control circuit of a display. In the method operated in the circuit system, when an image is received, the pixel values of each of the regions divided from the image can be counted so as to obtain a local maximum and a local average of every region, and a global average of the image. The region having a dark-field halo can be detected based on a local difference between the local maximum and the local average. A leakage level can be obtained by determining an impact of the dark-field halo on the whole image based on a threshold. The leakage level and the global average are referred to for calculating a gain for global backlight adjustment after performing local dimming.

Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.

Abstract: A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.

Abstract: An LC (inductor-capacitor) oscillator includes a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein: the source of the first NMOS transistor is shorted to the source of the first PMOS transistor; the source of the second NMOS transistor is shorted to the source of the second PMOS transistor; the first NMOS transistor and the second NMOS transistor are cross coupled via a first gate inductor and a first drain inductor; the first and second PMOS transistors are cross coupled via a second gate inductor and a second drain inductor; the first NMOS transistor and the first PMOS transistor are coupled via a first gate capacitor and a first drain capacitor; and the second NMOS transistor and the second PMOS transistor are coupled via a second gate capacitor and a second drain capacitor.

Abstract: A signal generator and a method for verifying an asynchronous interface circuit are provided, where the signal generator includes a frame modulator, a clock generator, an interface selector and a checking module. The frame modulator generates a modulated signal according to a frame control parameter, and the clock generator generates a clock signal according to a clock control parameter. The interface selector generate a receiving test signal according to an interface control parameter, the modulated signal and the clock signal, where the signal generator utilize a reference model to generate a reference signal according to the receiving test signal, and the asynchronous interface circuit generates a transmitting test signal according to the receiving test signal. In addition, the checking module generates at least one verification result according to the reference signal and the transmitting test signal.

Abstract: A time-to-digital converter and a calibration method for performing time-to-digital conversion on an input signal are provided. The time-to-digital converter includes a time counter, a calibration circuit and an adder. The time counter starts counting in response to a first edge of the input signal and stops counting in response to a second edge of the input signal, to generate a preliminary counting value. The calibration generates a first determination bit according to the first edge of the input signal and a first edge of a clock signal, generates a second determination bit according to the second edge of the input signal and a second edge of the clock signal, and generates a calibration value according to the first determination bit and the second determination bit. In addition, the adder adds the calibration value to the preliminary counting value to generate a final counting value.

Abstract: The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.

Abstract: The present invention provides an encoder including M core circuits. The M core circuits are configured to encode a first row of superblocks to a M-th row of superblocks of an image frame, and to update a cumulative distribution function (CDF) table during an encoding process of each superblock, where M is a positive integer greater than 1. The M core circuits are further configured to encode a (M+1)-th row of superblocks to a (2*M)-th row of superblocks of the image frame, and to update the CDF table during the encoding process of each superblock, wherein a first core circuit of the M core circuits uses the CDF table generated during the encoding process of a last superblock of the first row of superblocks to encode a first superblock of the (M+1)-th row of superblocks.

Abstract: A communication device includes a transceiver circuit for communicating with a network to perform a registration; and a processing circuit, coupled to the transceiver circuit, for performing a sleeping mode according to a first configuration from the network; receiving a first instruction from a user, wherein the first instruction configures the communication device to enter a high performance mode from the sleeping mode; ignoring the first configuration and entering the high performance mode from the sleeping mode according to the first instruction.

Abstract: A detection system and a detection method are provided. The detection method includes: receiving an image containing a face by an angle acquisition module and obtaining a first angle and a second angle of the face based on the image; obtaining a first projection value and a second projection value based on the first angle and the second angle by a projection calculation module; and performing by a confidence calculation module: performing an exponentiation calculation on the first projection value based on a first correction value to obtain a third value; performing an exponentiation calculation on the second projection value based on a second correction value to obtain a fourth value; and obtaining a confidence value based on the third value and the fourth value.

Abstract: A digital pre-distortion circuit includes a memoryless non-linear operating circuit, an intermodulation shaping filter circuit, and a signal combination circuit. The memoryless non-linear operating circuit performs a memoryless non-linear operation upon a transmission signal to generate a first signal, wherein the first signal is an output simulation signal of a radio frequency (RF) power amplifier under the memoryless effect, and the first signal includes a signal component corresponding to the transmission signal and a signal component corresponding to an intermodulation signal of the transmission signal. The intermodulation shaping filter circuit filters the first signal to generate a second signal, wherein the second signal simulates an intermodulation signal generated by the RF power amplifier in response to the transmission signal under a memory effect. The signal combination circuit combines the transmission signal and the second signal to generate a pre-distortion signal.

Abstract: A Class-D amplifier includes a loop filter circuit, a comparator circuitry, an output circuitry, and a common-mode control circuitry. The loop filter circuit generates first and second signals according to input and output signals and adjusts common-mode levels of the first and second signals according to a first common-mode signal. The comparator circuitry respectively compares a ramp signal with the first and second signals to generate pulse signals, and a common-mode level of the ramp signal is set based on a second common-mode signal. The output circuitry is powered by a power supply voltage to generate the output signals according to the pulse signals. The common-mode control circuitry performs an AC-coupling operation on the power supply voltage to generate a noise signal and generate one of the first and second common-mode signals according to the noise signal and another one of the first and second common-mode signals.

Abstract: A scheduling method of scheduling a target wake time (TWT) communication between an access point and at least one station. The scheduling method includes the access point adjusting a broadcast TWT schedule according to a power saving setting, and the access point transmitting the broadcast TWT schedule. The broadcast TWT schedule includes a broadcast TWT SP start time, a broadcast TWT service period and a broadcast TWT interval.

Abstract: The disclosure provides a radio frequency rectifier device, including a first input node, a first capacitor, a second input node, a second capacitor, a first transistor element, a second transistor element, a third capacitor, a fourth capacitor, a third transistor element, a fourth transistor element, a fifth capacitor, a sixth capacitor, a first conductive element, a second conductive element, a third conductive element, a fourth conductive element, a load resistor and a load capacitor. When the first conduction element, the second conduction element, the third conduction element and the fourth conduction element are turned on, a gate voltage of the first transistor element, a gate voltage of the second transistor element, a gate voltage of the third transistor element and a gate voltage of the fourth transistor element are reduced respectively. These operations reduce a leakage current and a discharge interval of the transistor element, thereby improving power conversion efficiency.

Abstract: A transconductance gain calibration circuit includes a constant voltage source, a first transconductance amplifier, a second transconductance amplifier, and a comparison module. The constant voltage source is configured to generate a reference voltage. The first transconductance amplifier responds to the reference voltage to produce a constant current. The second transconductance amplifier responds to the reference voltage to produce a variation current. The comparison module includes a first potentiometer, a reference resistor, and a comparison circuit. The first potentiometer is coupled to the first transconductance amplifier and is configured to generate a variation voltage based on the constant current and an adjustable resistance. The reference resistor is coupled to the second transconductance amplifier and is configured to generate a constant voltage based on the variation current and a designed resistance value.

Abstract: A differential sampling circuit is configured to sample a differential circuit. The differential circuit includes a first output and a second output, and the differential sampling circuit includes an amplifier and a switch circuit. The switch circuit includes a capacitor, a pair of sampling switches, and a pair of output switches. One end of the capacitor is coupled to the first output of the differential circuit through one of the pair of sampling switches, and is coupled to a reference terminal through the one of the pair of output switches. The other end of the capacitor is coupled to the second output of the differential circuit through the other of the pair of sampling switches, and is coupled to an input terminal of the amplifier through the other of the pair of output switches.