Abstract: A detection system and a detection method are provided. The detection method includes: receiving an image containing a face by an angle acquisition module and obtaining a first angle and a second angle of the face based on the image; obtaining a first projection value and a second projection value based on the first angle and the second angle by a projection calculation module; and performing by a confidence calculation module: performing an exponentiation calculation on the first projection value based on a first correction value to obtain a third value; performing an exponentiation calculation on the second projection value based on a second correction value to obtain a fourth value; and obtaining a confidence value based on the third value and the fourth value.

Abstract: A communication device includes a transceiver circuit for communicating with a network to perform a registration; and a processing circuit, coupled to the transceiver circuit, for performing a sleeping mode according to a first configuration from the network; receiving a first instruction from a user, wherein the first instruction configures the communication device to enter a high performance mode from the sleeping mode; ignoring the first configuration and entering the high performance mode from the sleeping mode according to the first instruction.

Abstract: A digital pre-distortion circuit includes a memoryless non-linear operating circuit, an intermodulation shaping filter circuit, and a signal combination circuit. The memoryless non-linear operating circuit performs a memoryless non-linear operation upon a transmission signal to generate a first signal, wherein the first signal is an output simulation signal of a radio frequency (RF) power amplifier under the memoryless effect, and the first signal includes a signal component corresponding to the transmission signal and a signal component corresponding to an intermodulation signal of the transmission signal. The intermodulation shaping filter circuit filters the first signal to generate a second signal, wherein the second signal simulates an intermodulation signal generated by the RF power amplifier in response to the transmission signal under a memory effect. The signal combination circuit combines the transmission signal and the second signal to generate a pre-distortion signal.

Abstract: A Class-D amplifier includes a loop filter circuit, a comparator circuitry, an output circuitry, and a common-mode control circuitry. The loop filter circuit generates first and second signals according to input and output signals and adjusts common-mode levels of the first and second signals according to a first common-mode signal. The comparator circuitry respectively compares a ramp signal with the first and second signals to generate pulse signals, and a common-mode level of the ramp signal is set based on a second common-mode signal. The output circuitry is powered by a power supply voltage to generate the output signals according to the pulse signals. The common-mode control circuitry performs an AC-coupling operation on the power supply voltage to generate a noise signal and generate one of the first and second common-mode signals according to the noise signal and another one of the first and second common-mode signals.

Abstract: A scheduling method of scheduling a target wake time (TWT) communication between an access point and at least one station. The scheduling method includes the access point adjusting a broadcast TWT schedule according to a power saving setting, and the access point transmitting the broadcast TWT schedule. The broadcast TWT schedule includes a broadcast TWT SP start time, a broadcast TWT service period and a broadcast TWT interval.

Abstract: The disclosure provides a radio frequency rectifier device, including a first input node, a first capacitor, a second input node, a second capacitor, a first transistor element, a second transistor element, a third capacitor, a fourth capacitor, a third transistor element, a fourth transistor element, a fifth capacitor, a sixth capacitor, a first conductive element, a second conductive element, a third conductive element, a fourth conductive element, a load resistor and a load capacitor. When the first conduction element, the second conduction element, the third conduction element and the fourth conduction element are turned on, a gate voltage of the first transistor element, a gate voltage of the second transistor element, a gate voltage of the third transistor element and a gate voltage of the fourth transistor element are reduced respectively. These operations reduce a leakage current and a discharge interval of the transistor element, thereby improving power conversion efficiency.

Abstract: A transconductance gain calibration circuit includes a constant voltage source, a first transconductance amplifier, a second transconductance amplifier, and a comparison module. The constant voltage source is configured to generate a reference voltage. The first transconductance amplifier responds to the reference voltage to produce a constant current. The second transconductance amplifier responds to the reference voltage to produce a variation current. The comparison module includes a first potentiometer, a reference resistor, and a comparison circuit. The first potentiometer is coupled to the first transconductance amplifier and is configured to generate a variation voltage based on the constant current and an adjustable resistance. The reference resistor is coupled to the second transconductance amplifier and is configured to generate a constant voltage based on the variation current and a designed resistance value.

Abstract: A differential sampling circuit is configured to sample a differential circuit. The differential circuit includes a first output and a second output, and the differential sampling circuit includes an amplifier and a switch circuit. The switch circuit includes a capacitor, a pair of sampling switches, and a pair of output switches. One end of the capacitor is coupled to the first output of the differential circuit through one of the pair of sampling switches, and is coupled to a reference terminal through the one of the pair of output switches. The other end of the capacitor is coupled to the second output of the differential circuit through the other of the pair of sampling switches, and is coupled to an input terminal of the amplifier through the other of the pair of output switches.

Abstract: A method and a system for setting a digital equalizer are provided. The method and the system are applicable to a signal receiver. The signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, and the target digital equalizer has an equalizer coefficient. The method includes: obtaining, during a simulation phase, a plurality of coefficient initial values and a plurality of coefficient limit values that respectively correspond to a plurality of preset transmission channels; and setting, during a connection phase, the equalizer coefficient of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels.

Abstract: A neural network system and an operation method for a neural network system are provided. The neural network system includes at least one edge device and a server. Each edge device stores a neural network architecture. The neural network architecture includes at least one operator and a model identifier, and the at least one operator of the neural network architecture stored in the each edge device includes an operator identifier. The server is connected to the each edge device. The each edge device is configured to, upon being powered on, transmit the operator identifier of each operator to the server to request the server to return parameters for the each operator; receive the parameters of the each operator and combine the parameters of the each operator with the neural network architecture to obtain a neural network model; and execute a predetermined task based on the neural network model.

Abstract: A method for configuring network traffic and a computer system are provided. The computer system includes a processing unit and a network module that is operated based on a bandwidth configuration. The processing unit operates an operating system that executes a profiling-controlling program. The method is performed in the operating system. In the method, the operating system initiates a system kernel, and the profiling-controlling program can obtain kernel operation information from the system kernel, so that information of multiple applications operating in a foreground process and a background process of the operating system can be retrieved. A priority order is decided, and a network bandwidth configuration is formed and written into traffic control instructions of the system kernel or a driver of the network module. The network bandwidth configuration allows the operating system to perform a traffic configuration on each of the applications.

Abstract: A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Abstract: A communication device respectively establishes a plurality of wireless communication connections with a plurality of predetermined devices in an infrastructure network, and includes a wireless transceiver and a processor. The wireless transceiver transmits or receives wireless signals. The processor selects a spatial reuse mechanism, generates spatial reuse information according to the spatial reuse mechanism, and transmits at least one packet carrying the spatial reuse information to the predetermined devices. The spatial reuse information defines a pattern of a communication period. The communication period comprises a spatial reuse phase and a non-spatial reuse phase. The spatial reuse information comprises time information of at least one of the spatial reuse phase and the non-spatial reuse phase. In response to a selection of the spatial reuse mechanism, the processor suspends a wireless signal transmission with the predetermined devices during the spatial reuse phase.

Abstract: A controlling device for handling a low latency transmission includes: a storage module, for maintaining a list, wherein the list includes a plurality of transmission information of a plurality of transmitting devices, and the plurality of transmission information includes a plurality of statuses, a plurality of priorities and a plurality of airtime resources, wherein each of the plurality of priorities indicates a priority level of a plurality of priority levels; and a scheduling module, coupled to the storage module, for generating a high priority window, and selecting a transmitting device from the plurality of transmitting devices in the high priority window according to the plurality of statuses, the plurality of priorities and the plurality of airtime resources to control the transmitting device to perform a transmission.

Abstract: A cloud gaming terminal device includes a playback quality evaluation unit and a feedback engine client. The playback quality evaluation unit is configured to generate at least one playback quality evaluation parameter based on information provided by at least one of a network interface control unit, a media decoding unit, and a media rendering unit within the cloud gaming terminal device. The feedback engine client is configured to transmit at least one playback quality evaluation parameter to a cloud gaming server through a network. The cloud gaming server is configured to adjust at least one media encoding parameter of a media stream according to the received playback quality evaluation parameter.

Abstract: The present invention provides a method for testing a chip, which includes the steps of: receiving a clock signal and a data signal from a verification module; shaping the clock signal and/or the data signal to generate a constructed clock signal and a constructed data signal; inputting the constructed clock signal and the constructed data signal into the chip; receiving an output clock signal and an output data signal from the chip; and performing timing checks on the output clock signal and the output data signal to generate an output check clock signal and a checked data signal to the verification module.

Abstract: A method for controlling a wireless communication module includes: causing the wireless communication module to establish a first connection and a second connection with a plurality of specific wireless communication modules, respectively; respectively maintaining a first timer for a first connection port corresponding to the first connection and a second timer for a second connection port corresponding to the second connection; selecting a target port from the first connection port and the second connection port according to a request from an application program interface corresponding to the wireless communication module; and in response to the request from the application program interface, returning a time value provided by the timer corresponding to the target port.

Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: A method for displaying a video stream on a display device with a variable refresh rate function is provided. The method includes: receiving the video stream and decoding the video stream to generate a plurality of decoded video frames; determining a frame ready time for each of the decoded video frames; determining a frame display time for each of the decoded video frames; determining a target refresh rate for the display device based on a frame latency between the frame ready time and the frame display time corresponding to at least one of the decoded video frames; and controlling the display device to display the video stream at the target refresh rate.

Abstract: A data dumping circuit is coupled to a combinational logic circuit, and includes a sensing and locking circuit and a scan chain circuit. The sensing and locking circuit is arranged to sense a characteristic value of the combinational logic circuit, and generate a scan enabling signal in response to the characteristic value being determined to be changed. The scan chain circuit is coupled to multiple flip-flops, and operates in a scan mode in response to the scan enabling signal, wherein in the scan mode, the scan chain circuit sequentially outputs a value stored in each of the multiple flip-flops for acting as dumping data.