Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

Abstract: A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.

Abstract: A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.

Abstract: The present invention provides a speed detection circuit positioned in a chip, wherein the speed detection circuit includes a test signal generator, a launch flip-flop, a device under test (DUT), a capture flip-flop, a comparator and a control circuit. The test signal generator is configured to generate a test signal with a specific pattern. The launch flip-flop is configured to use a first clock signal to sample the test signal to generate a sampled test signal. The device under test is configured to receive the sampled test signal to generate a delayed test signal. The capture flip-flop is configured to use a second clock signal to sample the delayed test signal to generate an output signal. The comparator is configured to determine whether the output signal conforms to the specific pattern to generate a comparison result, for the control circuit to determine a speed of the chip.

Abstract: The present invention provides a packet forwarding system including a packet, a packet analyzer and a DMA module. The packet buffer is configured to receive a packet and store the packet. The packet analyzer is configured to read the packet from the packet buffer, and analyze the packet to extract part of content of the packet to generate specific data. The DMA module is configured to write the specific data into a first buffer of a storage device, and write the packet into a second buffer of the storage device.

Abstract: A method for performing media playback on a media playback device includes: generating a quick launch area in a user interface according to a quick launch setting, wherein the quick launch area includes a plurality of windows, and the windows correspond to at least one audio-visual (AV) content and at least one application program respectively; according to the quick launch setting, retrieving data corresponding to the at least one AV content and buffering the data in a first buffering unit; according to the quick launch setting, retrieving data required by executing the at least one application program and buffering the data in a second buffering unit; and in response to a quick launch operation, decoding the data buffered in the first buffering unit to play the AV content, or utilizing the data buffered in the second buffering unit to execute the at least one application program.

Abstract: A display control method includes: receiving a first video signal provided by a first video source device to display one or more first images in the first video signal on a display device; when the display device is displaying the one or more first images, establishing a connection with a second video source device and receiving a second video signal provided by the second video source device through the connection; generating one or more composite images based on the one or more first images in the first video signal and one or more second images in the second video signal without receiving a user control input; and displaying the one or more composite images on the display device.

Abstract: A card reader and a controller thereof, and a method are provided. The card reader includes a storage device and the controller, wherein the controller is coupled to the storage device. The storage device is configured to store specific identification data of a specific memory device. The controller is configured to receive identification data of the external memory device plugged into the card reader, and determine whether the external memory device is the specific memory device according to the identification data and the specific identification data, to generate a determination result. More particularly, the controller may control whether to open permission of at least one function according to the determination result.

Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device, a first Bluetooth member device, and a second Bluetooth member device. The audio broadcasting device broadcasts BLE audio packets and transmits a predetermined volume instruction to the first Bluetooth member device and the second Bluetooth member device before broadcasting the BLE audio packets. The first Bluetooth member device parses the BLE audio packets to acquire a predetermined audio data, controls a first audio playback circuit to playback the predetermined audio data, and configures an audio volume of the first audio playback circuit in advance according to the predetermined volume instruction. The second Bluetooth member device parses the BLE audio packets to acquire the predetermined audio data, controls a second audio playback circuit to playback the predetermined audio data, and configures an audio volume of the second audio playback circuit in advance according to the predetermined volume instruction.

Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device, a first Bluetooth member device, and a second Bluetooth member device. The audio broadcasting device broadcasts BLE audio packets and transmits a volume adjusting instruction to the first Bluetooth member device and the second Bluetooth member device after they receive the BLE audio packets. The first Bluetooth member device parses the BLE audio packets to acquire a predetermined audio data, controls a first audio playback circuit to playback the predetermined audio data, and adjusts an audio volume of the first audio playback circuit according to the volume adjusting instruction. The second Bluetooth member device parses the BLE audio packets to acquire the predetermined audio data, controls a second audio playback circuit to playback the predetermined audio data, and adjusts an audio volume of the second audio playback circuit according to the volume adjusting instruction.

Abstract: A load balance circuit includes: a storing circuit, for storing first user field number(s) corresponding to first node(s) in a minimum full binary tree, wherein first resource unit(s) (RU(s)) corresponding to the first node(s) is smaller than or equal to an RU size; a user field number generation circuit, for generating third user field number(s) according to second user field number(s) corresponding to second node (s) in the minimum full binary tree, and generating second weight(s) according to first weight(s) corresponding to the second node(s), wherein second RU(s) corresponding to the second node(s) is greater than the RU size; and a load balance calculation circuit, for generating a plurality of user field numbers corresponding to a plurality of content channels according to the first user field number(s), the third user field number(s), the second weight(s), a load balance function and the first weight(s).

Abstract: A content channel generation device includes: a splitting circuit for generating resource units according to resource assignments; a resource unit assignment circuit for generating a full binary tree according to the resource units; a node computing circuit for generating a minimum full binary tree according to the full binary tree; a load balance circuit for generating user field numbers corresponding to content channels according to the minimum full binary tree and a load balance function; a merging circuit for generating a traversal result of the minimum full binary tree according to a traversal algorithm, and for generating a merged traversal result according to the traversal result; and a common field generation circuit for generating a resource assignment indicator according to the merged traversal result to generate a common field.

Abstract: The present invention provides a method for detecting a flash memory module and an associated SoC. The method reads data in a flash memory module with a specific data format, and then determining a plurality of characteristic parameters of the flash memory module and a size of a page by decoding and checking the data. Therefore, the SoC does not need to design a one-time-programmable memory or strap pins, so as to reduce the manufacturing cost of the SoC.

Abstract: A signal processing circuit includes an encoding circuit and a subcarrier sorting circuit. The encoding circuit is arranged to encode an input data to generate multiple codewords corresponding to a symbol. The subcarrier sorting circuit is arranged to sequentially arrange multiple subcarriers into an array, wherein a size of the array is M*N, N is a number of columns, N is equal to a number of the multiple codewords corresponding to the symbol, M is a number of rows, and M is a number of the multiple subcarriers divided by N; and the multiple subcarriers are sequentially arranged into the array starting from a row of the array, and subcarriers comprised in each column of the array are arranged to transmit one of the multiple codewords.

Abstract: A logic circuit and a method for checking and updating program counter (PC) values in a pipeline architecture are provided. The logic circuit includes a checking circuit and a PC value determination circuit. The checking circuit checks a continuity of a current PC value and multiple flags related to a branch predictor, in order to generate a checking result, where the branch predictor is configured to control the multiple flags according to the current PC value. The PC value determination circuit selects one of multiple candidate PC values to be a subsequent PC value according to the checking result, where the current PC value corresponds to a current instruction, and the subsequent PC value corresponds to a subsequent instruction after the current instruction.

Abstract: An optimization method for an implementation of mel-frequency cepstral coefficients is provided. The optimization method includes the following steps: performing a framing step, including using a 400×16 static random access memory to temporarily store a plurality of sampling points of a sound signal with overlap, and decomposing the sound signal into a plurality of frames. Each of the plurality of frames is 400 of the sampling points, there is an overlapping region between adjacent two of the plurality of frames, and the overlapping region includes 240 of the sampling points. The optimization method further includes performing a windowing step, which includes multiplying each of the plurality of frames by a window function in a bit-level design, and the optimization method includes performing a fast Fourier transform (FFT) step, which includes applying a 512 point FFT on a frame signal to obtain a corresponding frequency spectrum.

Abstract: An integrated circuit apparatus and a power distribution network thereof are provided. The power distribution network includes a top wiring layer, a bottom wiring layer, and a first conductive path. The top wiring layer includes a first top trace and a second top trace extending along a first direction. The bottom wiring layer includes a first bottom trace extending along a second direction. The first bottom trace has an electric potential equal to that of the first top trace, but different from that of the second top trace. The first conductive path connected between the first top and bottom traces includes a first upper conductive structure and a first lower conductive structure that are located directly under the first top trace and the second top trace, respectively. A signal wire preselected region is defined between the first upper conductive structure and the first bottom trace.

Abstract: A firmware updating system and method are provided. The firmware updating method includes configuring a host to digitally sign a firmware to be updated, and configuring an electronic device to perform an authorization verification on an update tool, and only the update tool that passes the verification has an update permission. The update tool uses an encryption algorithm to encrypt the firmware to be updated that includes a digital signature. After the encryption is completed, the host sends the update tool to the electronic device through the update tool. The electronic device then uses a decryption algorithm to decrypt the received firmware to obtain the firmware to be updated including the digital signature, and write the firmware to be updated into a firmware storage area to be updated. The electronic device then verifies the digital signature in the firmware to be updated.

Abstract: An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.

Abstract: A communications device and a method for receiving an aggregate packet are provided. The communications device includes an aggregate packet de-aggregation device and a transmission interface. The aggregate packet de-aggregation device is configured to generate multiple subframe packets according to the aggregate packet, wherein a length of each of the multiple subframe packets is less than a length of the aggregate packet. The transmission interface is configured to couple the communications device to a host device, and transmits the multiple subframe packets to the host device, to allow the host device to pre-allocate multiple buffering spaces for receiving the multiple subframe packets according to a maximum allowable length of any of the multiple subframe packets.