Abstract: The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N?n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Abstract: A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

Abstract: An audio-visual managing system, applied to at least one data receiving circuit which receives audio-visual data and outputs processed audio-visual data, each of the data receiving circuit comprising a tuner or a demodulator, the audio-visual managing system comprising: a plurality of transmitting circuits, configured to stream the processed audio-visual data; wherein the processed audio-visual data output by a first data receiving circuit of the data receiving circuit can be used by a first transmitting circuit and a second transmitting circuit of the transmitting circuits simultaneously, when the first transmitting circuit and the second transmitting circuit receive the processed audio-visual data output by the first data receiving circuit.

Abstract: A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.

Abstract: A method for controlling operations of an asynchronous FIFO memory includes: determining a current depth of the asynchronous FIFO memory according to at least one of a clock ratio, a burst length and a continuous transmission length, where the clock ratio is a ratio of a frequency of a first clock signal used by a master device to a frequency of a second clock signal used by a slave device; configuring one or more entries of the asynchronous FIFO memory to be used according to the current depth; and controlling a plurality of FIFO clock signals provided to the asynchronous FIFO memory according to the current depth. One FIFO clock signal corresponds to one entry, and one or more FIFO clock signals corresponding to one or more entries that are not configured according to the current depth are disabled.

Abstract: A chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, and a control circuit. The I/O pins include a plurality of mapping pins and a control pin. The readable/writable memory includes a clock port, a plurality of I/O ports, and an enable port. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the clock port, the I/O ports, and the enable port to the mapping pins respectively.

Abstract: An image brightness adjusting method, comprising: (a) computing or predicting a first input frame rate according to at least one first input image; (b) generating a first brightness according to a first brightness curve and the first input frame rate, wherein the first brightness curve corresponds to a first frame rate; (c) generating a second brightness according to a second brightness curve and the first input frame rate, wherein the second brightness curve corresponds to a second frame rate; (d) generating a first brightness compensating curve according to the first input frame rate and a brightness difference between the first brightness and the second brightness; and (e) setting a first compensating brightness of at least one second input image according to the first brightness compensating curve.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: A scheduling method of scheduling a target wake time (TWT) communication between an access point and at least one station. The scheduling method includes the access point adjusting a broadcast TWT schedule according to a power saving setting, and the access point transmitting the broadcast TWT schedule. The broadcast TWT schedule includes a broadcast TWT SP start time, a broadcast TWT service period and a broadcast TWT interval.

Abstract: A method for calibrating compensation values utilized by a compensation device in a transmitter includes: obtaining a plurality of output signals sequentially generated by the transmitter by processing a pair of input signals based on a plurality of pairs of compensation values as a plurality of feedback signals, where each feedback signal corresponds to one of the plurality of pairs of compensation values; obtaining a signal component of the feedback signals at a predetermined frequency as a portion of the feedback signals; determining a pair of equivalent impairment parameters in a calibration operation according to the plurality of pairs of compensation values and the portion of the feedback signals; and determining a pair of calibrated compensation values according to the pair of equivalent impairment parameters and providing the pair of calibrated compensation values to the compensation device.

Abstract: A signal detection circuit is provided, and includes an input switch circuit, an amplitude detection circuit, a clock generating circuit, and an integration circuit. The input switch circuit receives a reference voltage and an input voltage and selectively outputs the reference voltage or the input voltage. The amplitude detection circuit detects an output of the input switch circuit to generate an amplitude voltage. The clock generating circuit controls the input switch circuit to alternately enter first and second phases, the input switch circuit is controlled to output the reference voltage in the first phase, and output the input voltage in the second phase. The integration circuit receives the amplitude voltage as an input, and generates an integration voltage corresponding to an accumulation result within a predetermined time interval. The predetermined time interval includes at least one period that cycles between the first phase and the second phase.

Abstract: A method and a system for compensating an image having fixed pattern noise are provided. The method is adapted to a 4-cell sensor and can automatically calculate appropriate compensation parameters for fixed pattern noise according to non-uniformity of the sensor and lens. Since the defects in the sensor or the lens may cause non-uniform fixed pattern noise, an image is firstly divided into multiple grids and a pixel average of every channel in the grids is calculated. Afterwards, a fixed pattern noise compensation coefficient of every pixel can be calculated according to characteristics of the image formed by the 4-cell sensor. In one aspect, the compensation coefficient of the current pixel can be calculated by extrapolation or interpolation. The fixed pattern noise in the image can be corrected.

Abstract: A controlling device for handling a low latency transmission includes: a storage module, for maintaining a list, wherein the list includes a plurality of transmission information of a plurality of transmitting devices, and the plurality of transmission information includes a plurality of statuses, a plurality of priorities and a plurality of airtime resources, wherein each of the plurality of priorities indicates a priority level of a plurality of priority levels; and a scheduling module, coupled to the storage module, for generating a high priority window, and selecting a transmitting device from the plurality of transmitting devices in the high priority window according to the plurality of statuses, the plurality of priorities and the plurality of airtime resources to control the transmitting device to perform a transmission.

Abstract: An amplifier system includes an output circuit, a processor circuit, a feedback circuit, and a controller circuit. The output circuit outputs an output signal and returns a digital output feedback signal. The processor circuit receives a filtered error audio signal and outputs a pulse width modulation control signal to the output circuit. An addition unit of the feedback circuit adds the negative value of the digital output feedback signal to the digital input signal to obtain the error audio signal. A variable filter unit of the feedback circuit filters the error audio signal and outputs the filtered error audio signal. A compensation unit of the variable filter unit changes the gain characteristics of the variable filter unit. The controller circuit adjusts one or more parameters of the compensation unit according to a pre-compensation signal so as to change the gain characteristics of the variable filter unit.

Abstract: A data accessing method includes providing a first memory including a plurality of memory pages, acquiring a usage order value of each memory page of the plurality of memory pages, acquiring a first usage order value having a highest priority from a plurality of usage order values corresponding to the plurality of memory pages in the first memory, updating the first memory after a first memory page having the first usage order value is used, acquiring a second usage order value having a highest priority from the updated first memory after the first memory is updated, and using a second memory page having the second usage order.

Abstract: An input/output port circuit includes an input/output pad, a transistor, and a conductive routing wire. The transistor has a first connection terminal and a second connection terminal. The first connection terminal of the transistor is electrically connected to the input/output pad through a conductive connection wire, and the second connection terminal is electrically connected to another transistor. The conductive routing wire is electrically connected to the first terminal of the transistor. The conductive routing wire is configured to provide a serial resistance, thereby forcing a surge current to flow toward the another transistor when the surge current is inputted in the input/output circuit through the input/output pad.

Abstract: A method for authentication data transmission and a system thereof are provided. The method is operated in a computer system that is connected to a biometric device, and a secure channel is established there-between according to a security protocol. The computer system can receive encrypted biometric feature data from the biometric device based on a request. In a secure environment built in the computer system, the biometric feature data is decrypted and biometric features can be extracted. A comparison result is generated after comparing the biometric features with feature data in a database. The comparison result can be transmitted to the biometric device. The comparison result is then encrypted in the biometric device according to the security protocol. The biometric device can therefore transmit the encrypted comparison result to the computer system via the secure channel.

Abstract: A method for adjusting a target clock of a wireless device and a wireless device thereof are provided. The method includes receiving two consecutive broadcast packets from a transmitter to obtain time information corresponding to each of the two broadcast packets; obtaining a time interval between the two broadcast packets according to the time information; and adjusting the target clock of the wireless device according to the time interval and a target value, to achieve the effect of automatically adjusting the target clock, the target clock being related to waking of the wireless device from a standby mode.

Abstract: A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.