Abstract: A method for processing a static pattern in an image and a circuit system are provided. In the method, each of frames of a video is divided into multiple areas. Several algorithms are used to calculate a static pattern index of every area. The static pattern index is used as a reference for determining if the area covers part or entire of a static pattern. An index threshold can be used to check the areas that are determined as the static pattern initially. A time threshold is then used to confirm the areas with the static pattern in every frame. Image data of the areas which are determined as the static patterns can then be adjusted, such as having brightness of the area that is determined as part or entire of the static patterns decreased, for preventing the display panel from negative effects of the static pattern.

Abstract: The present invention provides an audio control circuit comprising an USB interface and a processing circuit is disclosed. The USB interface is used to connect to a host device, and the processing circuit is configured to perform enumeration with the host device via the USB interface, and the processing circuit is further configured to determine if the host device operates in a BIOS stage or an operating system stage to generate a control signal according to packets of the enumeration. When the processing circuit determines that the host device operates in the BIOS stage, the processing circuit generates the control signal to enable a de-pop circuit; and when the processing circuit determines that the host device operates in the operating system stage, the processing circuit generates the control signal to disable the de-pop circuit.

Abstract: The present invention provides an image processing circuit including a receiving circuit, a reference value calculating circuit, a center luminance value calculating circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data. The reference value calculating circuit determines a first reference value and a second reference value corresponding to a plurality of pixels of the image data. The center luminance value calculating circuit refers to the first reference value and the second reference value to generate a center luminance value. The output circuit determines output luminance values of the plurality of pixel values according to the image data, the first reference value and the second reference value.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device generates a first cypher key according to an instruction from the first member device and a device information of the first member device after receiving a selection command. The first member device establishes a connection with the Bluetooth host device, and generates a second cypher key corresponding to the first cypher key according to a device information of the Bluetooth host device.

Abstract: A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit and a phase control circuit. The phase detector samples input data signal according to first clock signals to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device generating a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device generating a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates second clock signals according to the frequency control signal. The phase control circuit controls phases of the second clock signals according to the phase control signal to generate the first clock signals.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: A signal compensation device includes a first receiving circuit, a second receiving circuit, a first buffer, a second buffer, a third buffer, and a processing circuit. The first receiving circuit receives a first video signal from a first video source. The second receiving circuit receives a second video signal from a second video source, wherein both the first video signal and the second video signal correspond to a same program. The first buffer stores a first transport stream (TS) packet group corresponding to the first video signal. The second buffer stores a second TS packet group corresponding to the second video signal. The processing circuit dynamically stores a first TS packet of the first TS packet group or a second TS packet of the second TS packet group to the third buffer according to a predetermined source in response to TS packet status.

Abstract: A neural network system and an operation method for a neural network system are provided. The neural network system includes at least one edge device and a server. Each edge device stores a neural network architecture. The neural network architecture includes at least one operator and a model identifier, and the at least one operator of the neural network architecture stored in the each edge device includes an operator identifier. The server is connected to the each edge device. The each edge device is configured to, upon being powered on, transmit the operator identifier of each operator to the server to request the server to return parameters for the each operator; receive the parameters of the each operator and combine the parameters of the each operator with the neural network architecture to obtain a neural network model; and execute a predetermined task based on the neural network model.

Abstract: A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.

Abstract: A method for retrieving a program data and a circuit system thereof are provided. The method that uses a dynamic packet identifier (PID) filter to retrieve the program data can be applied to a digital TV system. In the method, a master guide table is retrieved from a transport stream of digital TV signals, and a parsing method is executed to obtain a series of the PIDs. A polling method is used to obtain the program data corresponding to each of the PIDs. A filter window is applied to scan the PIDs for polling the program data corresponding to each of a group of the PIDs at once. After that, the filter window is shifted to a next group of the PIDs for polling the program data with respect to each of the PIDs, and an electronic program guide is accordingly formed.

Abstract: A multi-member Bluetooth device for communicating data with a remote Bluetooth device is disclosed including: a main Bluetooth circuit and an auxiliary Bluetooth circuit. In the period during which the auxiliary Bluetooth circuit operates at a relay mode, the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device and forwards the received packets to the auxiliary Bluetooth circuit; the auxiliary Bluetooth circuit does not sniff packets issued from the remote Bluetooth device, but will switch to a sniffing mode if a signal reception quality indicator of the auxiliary Bluetooth circuit is superior to a predetermined indicator value. In the period during which the auxiliary Bluetooth circuit operates at the sniffing mode, the auxiliary Bluetooth circuit sniffs packets issued from the remote Bluetooth device and the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device.

Abstract: A PWM-based (pulse width modulation-based) overcurrent protection circuit and an operating method for the same are provided. The PWM-based overcurrent protection circuit includes a pulse-width-modulation circuit that is connected to a charge pump and a load detection circuit of a power-switch circuit. The charge pump outputs a voltage to the power-switch circuit according to a clock-voltage signal. The load detection circuit is used to detect an overcurrent flowing through the power-switch circuit according to a load at an output end of the power-switch circuit. Thus, when the load detection circuit detects the overcurrent, the pulse-width-modulation circuit controls a duty-cycle width of the charge pump, so as to suppress the voltage outputted by the charge pump. Therefore, an output voltage from the power-switch circuit can be corrected for preventing or reducing the overcurrent.

Abstract: An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.

Abstract: An audio real-time processing system, an audio real-time processing program product and method for training speech analysis model are provided. The speech analysis model is firstly trained to obtain, from an original audio, mask information which is used to mask the original audio to get a target audio. The system obtains a plurality of analyzed audio according to the target audio and the original audio, obtains repeated audio section according to the plurality of the analyzed and output the repeated audio section.

Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.

Abstract: A television includes a remote control, a receiving element, a speaker, a speech analysis model, and a processor. The processor analyzes video sound to get a repeated audio section after receiving a volume adjustment command from the remote control. Then, the speaker outputs the repeated audio. So that, according to user needs, the television adjusts the video sound before outputting.

Abstract: An image processing method and a display device are provided. The image processing method is suitable for the display device. The display device includes an image processor and a panel module. The image processing method includes: when the image processor receives a notification signal from a source to switch the display format, the image processor stores a current image frame in a memory. The image processor provides the current image frame to the panel module, so that the panel module displays the current image frame. The image processor is re-handshaking with the source and the panel module to receive a new image frame provided by the source, and the image processor transmits the new image frame to the panel module, so that the panel module displays the new image frame.

Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.

Abstract: The present invention provides a method for accessing a system memory, wherein the method includes the steps of: reading a descriptor from the system memory, where the descriptor includes a buffer start address field and a buffer size field, wherein the buffer start address field includes a start address of a buffer in the system memory, and the buffer size field indicates a size of the buffer; receiving multiple packets, and writing the multiple packets in to the buffer; modifying the descriptor according to the multiple packets stored in the buffer to generate a modified descriptor, wherein the modified descriptor only comprises information of part of the multiple packets or does not comprise information of any one of the multiple packets; and writing the modified descriptor into the system memory.

Abstract: A joint test action group transmission system includes a host terminal and a slave terminal. The slave terminal includes a test access port (TAP) circuit, an internal memory, and a memory interface controller. The TAP circuit includes a test data register set. The memory interface controller stores the data received from the TAP circuit to the internal memory. The host terminal transmits a set of download instruction bits to the TAP circuit to have the TAP circuit select the test data register set, and have the TAP circuit enter a data shift status to receive a data package through the test data register set. During the process of receiving the data package, the TAP circuit remains in the data shift status to receive the address and at least one piece of data stored in the data package continuously.