Abstract: The present invention provides a control method applied to an electronic device is disclosed, wherein the electronic device includes a processor and a wireless network module, and the control method includes the steps of: generating a determination result by determining if the wireless network module needs to transmit a packet; and when the determination result indicates that the wireless network module needs to transmit the packet, reducing a frequency of a clock signal used by the processor during a packet transmission.

Abstract: A dynamic amplifier includes a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current into an output current to an output current; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate-resetting voltage; a third switch configured to conditionally connect the source node to a source-resetting voltage; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage.

Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Abstract: A measurement system for measuring a motion picture response time (MPRT) of a liquid crystal display (LCD) has a computer and a measurement device. The computer controls a display panel of the LCD to switch between a plurality of different gray levels. The measurement device measures variations of brightness of the display panel when the display panel switches its gray level. The computer obtains at least a gray level response time (GLRT) normalized curve according to results of measuring the variations of the brightness. The computer integrates the at least a GLRT normalized curve to obtain at least an MPRT normalized curve, obtains at least a time interval of the at least an MPRT normalized curve, and calculates an average of the at least a time interval to obtain the MPRT of the LCD.

Abstract: A debug system includes a chip to be tested and a debug controller. The chip to be tested includes a circuit to be tested, a debug access circuit and a debug protection circuit. When a protection function is not enabled, the debug protection circuit enables a communication between the debug access circuit and the chip to be tested, the debug controller accesses the data of the chip to be tested via the debug access circuit for debugging the circuit to be tested. When the protection function is enabled, the debug protection circuit blocks the communication between the debug access circuit and the chip to be tested, the debug controller transmits a message to the debug protection circuit via the debug access circuit, and the debug protection circuit determines whether to disable the protection function according to the message.

Abstract: An apparatus and a method for pipeline control are provided. The apparatus includes a preload predictor, an arithmetic logic unit (ALU) and a data buffer. The preload predictor is configured to determine whether a load instruction conforms to at least one specific condition, to generate a preload determination result. The ALU is configured to perform arithmetic logic operations, and the data buffer is configured to provide data for being used by the ALU. When the preload determination result indicates that the load instruction conforms to the at least one specific condition, the data buffer fetches preload data from a cache memory according to information carried by the load instruction and stores the preload data in the data buffer, where the preload data is data requested by a subsequent load instruction.

Abstract: A system is adapted to perform an image processing method. The processing method includes: obtaining input image data, a first training result, a second training result, and an interpolation lookup table; segmenting the input image data into a plurality of feature blocks according to a total quantity of area interpolations; establishing a position mapping relationship to record the feature blocks corresponding to positions of all of the area interpolations; assigning corresponding area interpolations to the feature blocks according to the position mapping relationship; obtaining an interpolation parameter for each of the feature blocks according to the first training result, the second training result, and the area interpolation; performing block convolution on each of the interpolation parameters and the corresponding feature block to obtain an output feature result; and obtaining an output image by combining the output feature results according to the position mapping relationship.

Abstract: The present invention provides a receiver including a filter, a signal detection circuit and a synchronization processing circuit. The filter is configured to filter a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal according to the filter input signal and the filter output signal, to generate an interference signal indicator; wherein when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal, the signal detection circuit further determines whether the filter output signal comprises an effective signal to generate an effective signal indicator. The synchronization processing circuit is configured to process the filter output signal according to the interference signal indicator and the effective signal indicator.

Abstract: A method for training a deep learning network for face recognition includes: utilizing a face landmark detector to perform face alignment processing on at least one captured image, thereby outputting at least one aligned image; inputting the at least one aligned image to a teacher model to obtain a first output vector; inputting the at least one captured image a student model corresponding to the teacher module to obtain a second output vector; and adjusting parameter settings of the student model according to the first output vector and the second output vector.

Abstract: A processing system is adapted to execute a method for testing power leakage of a circuit. The method includes: obtaining a plurality of undefined nets according to a netlist and power mode information; obtaining a trace path according to the undefined nets and the power mode information; and determining whether there is a risk of power leakage in the trace path, and outputting a testing result.

Abstract: A multi-stage amplifier includes a first stage comprising a first common-source amplifier, a first inductive load network comprising a serial connection of a first load resistor and a first load inductor, and a first source network configured to receive a first signal and output a first load signal, and a first inter-stage inductor configured to couple the first load signal to a second signal; and a second stage comprising a second common-source amplifier, a second inductive load network comprising a serial connection of a second load resistor and a second load inductor, and a second source network configured to receive the second signal and output a second load signal, and a second inter-stage inductor configured to couple the second load signal to a third signal, wherein the first load inductor and the second load inductor are laid out to enhance an inter-stage inductive coupling.

Abstract: A method of managing blocks in a flash memory includes: detecting states of blocks of a reserved area in the flash memory and building a bad block management table accordingly; recording mappings between bad blocks of an user area in the flash memory and good blocks of the reserved area into the bad block management table; when the bad block management table indicates there is no good block remaining in the reserved area that can be mapped to, selecting one of bad blocks of the reserved area or the user area and obtaining a recollected block after erasing the selected bad block; recording a mapping between the recollected block and a bad block in the user area into the bad block management table; and based on the bad block management table, programming data into the recollected block.

Abstract: A timing generator, a timing generating method and an associated control chip are provided, wherein the timing generator includes a receiving circuit, a transmitting circuit coupled to the receiving circuit, and a control unit respectively coupled to the receiving circuit and the transmitting circuit. The receiving circuit may be configured to receive a timing data set from a storage device. The transmitting circuit may be configured to select a specific signal type within multiple signal types according to the timing data set, and output an output signal having the specific signal type with a specific time length, wherein the timing data set indicates the specific signal type and the specific time length. The control unit may be configured to control operations of the receiving circuit and the transmitting circuit.

Abstract: Parameter calibration method for calibrating multiple parameters corresponding to multiple electronic components to be calibrated in a circuit, including steps: (A) turning off all of the electronic components to be calibrated and selecting a first electronic component from the electronic components to be calibrated as an electronic component being calibrated; (B) turning on the electronic component being calibrated and performing a calibration procedure on the electronic component being calibrated to determine a setting value of a parameter corresponding to the electronic component being calibrated; and (C) selecting a second electronic component from the electronic components to be calibrated as the electronic component being calibrated and performing step (B).

Abstract: A frame transmission method of an electronic device, wherein the frame transmission method includes the steps of: receiving a pause frame from another electronic device, wherein the pause frame includes a plurality of packet size ranges and corresponding pause times; referring to content of the pause frame, and determining a first frame interval according to which packet size range a first packet to be sent to the other electronic device belongs to; and after a first frame including the first packet is sent to said another electronic device, at least waiting for the first frame interval before starting to send a second frame to said another electronic device.

Abstract: A video signal processing device and method thereof are provided in the present application. The video processing device includes a storage and a processor. The storage stores a plurality of brightness mapping relationships. If set brightness corresponding to the brightness mapping relationships does not match the target brightness, the processor selects a first mapping relationship and a second mapping relationship of two pieces of set brightness closing to target brightness from the brightness mapping relationships. A target mapping relationship corresponding to the target brightness is obtained by an interpolation according to the first mapping relationship, the first brightness, the second mapping relationship and the corresponding set brightness. The processor converts nonlinear brightness information of a first video signal into linear brightness information of a second video signal according to the target mapping relationship.

Abstract: The present invention provides an image processing method, wherein the image processing method includes the steps of: using a plurality of corner detection filters to perform corner detection on a specific pixel of image data to generate a plurality of detection results, respectively, wherein the plurality of corner detection filters correspond to a plurality of corners with different directions, respectively; determining which one of the plurality of corners with different directions the specific pixel belongs to according to the plurality of detection results; and according to a specific corner among the plurality of corners to which the specific pixel belongs, performing an image processing operation corresponding to the specific corner on the specific pixel to generate processed image data.

Abstract: A communication device includes a radio transceiver and a collision detection device. The radio transceiver is configured to receive a wireless signal which includes an acknowledgment packet from a wireless communication channel. The acknowledgment packet includes acknowledgment information which corresponds to a plurality of transmitted packets. The collision detection device is coupled to the radio transceiver and configured to receive the acknowledgment packet, determine whether collision has occurred in the wireless communication channel according to the acknowledgment information corresponding to the transmitted packets and accordingly generate a detection result. The collision detection device determines whether collision has occurred according to a distribution of the acknowledgment information having a predetermined acknowledgment status.

Abstract: A method for real-time firmware configuration and a debugging apparatus are provided. When a demand for updating or debugging a target processor raises, in the method, a computer system generates a firmware debugging request that is attached with a firmware data with a specific debugging function. The computer system then loads the firmware data to a programmable logic unit of the debugging apparatus. After the real-time firmware configuration is completed, the computer system issues a debugging command to the programmable logic unit. The programmable logic unit obtains at least one debugging action after resolving the debugging command. The at least one debugging action is performed in the target processor when the target processor receives the at least one debugging action. A debugging result is returned after the at least one debugging action is completed.

Abstract: An analog front-end circuit capable of dynamically adjusting gain includes a programmable gain amplifier (PGA) circuit, a sensor, a calculation circuit, a gain coarse control circuit and a gain fine control circuit. The PGA circuit includes an amplifier, a gain coarse adjustment circuit and a gain fine adjustment circuit. The gain coarse adjustment circuit is controlled by a coarse control signal, and a gain is adjusted in a coarse step according to an initial gain. The gain fine adjustment circuit is controlled by a fine control signal in a data mode, and the gain is adjusted in a fine step. The calculation circuit calculates a primary gain adjustment and a secondary gain adjustment. The gain coarse control circuit generates the coarse control signal according to the primary gain adjustment, and the gain fine control circuit generates the fine control signal according to the secondary gain adjustment.