Patents Assigned to Realtek Semiconductor Corp.
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Publication number: 20250045222Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.Type: ApplicationFiled: July 31, 2024Publication date: February 6, 2025Applicant: Realtek Semiconductor Corp.Inventor: Chao-Min Lai
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Patent number: 12218674Abstract: A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.Type: GrantFiled: July 24, 2023Date of Patent: February 4, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chih-Yuan Yeh
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Patent number: 12217332Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.Type: GrantFiled: January 17, 2023Date of Patent: February 4, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Yu-Hsuan Hung, Chun-Fu Liao, Kai-Ting Shr
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Publication number: 20250038743Abstract: An isolated selector and an associated electronic device are provided. The isolated selector receives first data and second data from a first functional circuit and a second functional circuit, respectively, and the isolated selector includes an isolated component, wherein the isolated component receives the first data and generates isolated data according to a control signal and the first data. In addition, the isolated selector selects one of the first data and the second data to be output as output data of the isolated selector. When the isolated selector selects the second data to be output as the output data according to the control signal, the isolated component set the isolated data to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector.Type: ApplicationFiled: July 22, 2024Publication date: January 30, 2025Applicant: Realtek Semiconductor Corp.Inventors: Yu-Cheng Lo, Shu-Yu Chang
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Publication number: 20250038777Abstract: A digital pre-distortion circuit and a method for reducing clipping noise in a digital pre-distortion circuit are provided. The digital pre-distortion circuit includes a pre-distorter, a clipping logic, an error extraction circuit, a filter and a compensation circuit. The pre-distorter performs a pre-distortion operation according to an input signal to generate an initial pre-distortion signal, and the clipping logic clips the initial pre-distortion signal to generate a clipped pre-distortion signal. In addition, the error extraction circuit calculates a difference between the initial pre-distortion signal and the clipped pre-distortion signal to generate a clipped error signal, and the filter performs filtering on the clipped error signal to generate a filtered error signal, wherein the compensation circuit compensates the clipped pre-distortion signal according to the filtered error signal to generate an output signal.Type: ApplicationFiled: July 23, 2024Publication date: January 30, 2025Applicant: Realtek Semiconductor Corp.Inventor: Yuan-Shuo Chang
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Patent number: 12213195Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device is arranged to operably transmit an auto-pair request, a first device information corresponding to the first member device, and a second device information corresponding to the second member device to the Bluetooth host device. The Bluetooth host device is arranged to operably receive the auto-pair request, the first device information, and the second device information transmitted from the first member device. The Bluetooth host device is further arranged to operably establish a Bluetooth connection with the first member device and conduct pairing procedure with the first member device according to the auto-pair request.Type: GrantFiled: February 9, 2022Date of Patent: January 28, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Qing Gu, Bi Wei, Yu Hsuan Liu, Yung Chieh Lin, Cheng Cai, Sixian Wang
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Patent number: 12213196Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device is arranged to operably transmit a first device information corresponding to the first member device and a second device information corresponding to the second member device to the Bluetooth host device. The Bluetooth host device is arranged to operably receive the first device information and the second device information transmitted from the first member device. The Bluetooth host device is further arranged to operably establish a Bluetooth connection with the first member device and conduct pairing procedure with the first member device after receiving a selection command.Type: GrantFiled: February 9, 2022Date of Patent: January 28, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Qing Gu, Bi Wei, Yu Hsuan Liu, Yung Chieh Lin, Cheng Cai, Sixian Wang
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Patent number: 12211570Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.Type: GrantFiled: March 31, 2023Date of Patent: January 28, 2025Assignee: Realtek Semiconductor Corp.Inventors: Li-Wei Deng, Ying-Yen Chen, Chih-Tung Chen
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Patent number: 12212951Abstract: An audio system is proposed, dynamically playing optimized audio signals based on user position. A sensor circuits dynamically senses a target space to generate field context information. First speaker and second speaker are arranged for audio playback. A host device recognizes a user from the field context information, determines the user position corresponding to the target space, and adaptively assigns the user position as a target listening spot. A sensor circuit contains a camera capturing an ambient image out of the target space. A control circuit utilizes a user interface circuit to perform a configuration procedure which determines location, size and acoustic attribute information of an ambient object, and the control circuit accordingly performs a channel-based compensation operation on the target listening spot to generate optimized first channel audio signal and second channel audio signal.Type: GrantFiled: November 23, 2022Date of Patent: January 28, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Kai-Hsiang Chou
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Patent number: 12212761Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.Type: GrantFiled: February 8, 2023Date of Patent: January 28, 2025Assignee: Realtek Semiconductor Corp.Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Wei Li
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Publication number: 20250029902Abstract: A lead frame adapted to be applied to a quad flat no-lead (QFN) package structure is provided. The QFN package structure includes a die. Bumps are disposed on an active surface of the die. The lead frame includes a central region and a peripheral region surrounding the central region. The lead frame includes a plurality of leads. The leads are at the peripheral region. A solder pad is disposed on an upper surface of one of two ends of each of the leads. The solder pad of each of the leads is configured to be directly soldered to a corresponding one of the bumps on the active surface of the die. For each of the leads, the end having the solder pad is nearer to the central region of the lead frame with respect to the other end. A manufacturing method of semiconductor device is also provided.Type: ApplicationFiled: April 11, 2024Publication date: January 23, 2025Applicant: REALTEK SEMICONDUCTOR CORP.Inventor: Nai-Jen Hsuan
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Publication number: 20250030444Abstract: A digital pre-distortion circuit includes a memoryless non-linear operating circuit, an intermodulation shaping filter circuit, and a signal combination circuit. The memoryless non-linear operating circuit performs a memoryless non-linear operation upon a transmission signal to generate a first signal, wherein the first signal is an output simulation signal of a radio frequency (RF) power amplifier under the memoryless effect, and the first signal includes a signal component corresponding to the transmission signal and a signal component corresponding to an intermodulation signal of the transmission signal. The intermodulation shaping filter circuit filters the first signal to generate a second signal, wherein the second signal simulates an intermodulation signal generated by the RF power amplifier in response to the transmission signal under a memory effect. The signal combination circuit combines the transmission signal and the second signal to generate a pre-distortion signal.Type: ApplicationFiled: July 16, 2024Publication date: January 23, 2025Applicant: Realtek Semiconductor Corp.Inventors: Yuan-Shuo Chang, Shin-Lin Cheng
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Patent number: 12206578Abstract: An aggregation packet forwarding method and a system for the same are provided. The method includes: configuring a first NIC to transmit to-be-forwarded packets to an aggregation module; configuring the aggregation module to generate an aggregated packet according to packet characteristics of the to-be-forwarded packets; configuring a first processing unit to execute a first NIC driver to process the aggregated packet generated by the aggregation module and send them to an L2 forwarding module; configuring the L2 forwarding module to transmit the aggregated packet according to an L2 forwarding table; configuring a second processing unit to execute a second NIC driver to process the aggregated packet and send the aggregated packet to a deaggregation module; configuring the deaggregation module to deaggregate the aggregated packet into the to-be-forwarded packets, and send the to-be-forwarded packets to the second NIC; and configuring the second NIC to receive the to-be-forwarded packets.Type: GrantFiled: November 1, 2023Date of Patent: January 21, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chen-Wei Lee
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Patent number: 12207181Abstract: A first access point in a mesh network includes a transceiver and a processor. The processor is coupled to the transceiver, and is used to determine whether a second access point transmitting a beacon belongs to the mesh network upon detecting the beacon. If so, the processor is used to determine whether the beacon includes first channel switch announcement information, and if so, configure the transceiver to transmit second channel switch announcement information, and configure the first access point to switch to a target channel. The first channel switch announcement information and the second channel switch announcement information include information of the target channel.Type: GrantFiled: June 7, 2022Date of Patent: January 21, 2025Assignee: Realtek Semiconductor Corp.Inventor: Chien-Hung Liao
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Patent number: 12205667Abstract: The present invention provides a multi-die package including main die, a memory die, a first set of pins and a second set of pins. The main die includes a memory controller, a first set of pads, a second set of pads and a third set of pads. The memory die is coupled to the first set of pads and the second set of pads of the main die. The first set of pins is coupled to the third set of pads of the main die. The second set of pins is coupled to the second set of pads of the main die. The memory controller accesses the memory die through the first set of pads and the second set of pads, and the memory controller accesses a memory chip external to the multi-die package through the second set of pads and the third set of pads.Type: GrantFiled: September 28, 2022Date of Patent: January 21, 2025Assignee: Realtek Semiconductor Corp.Inventor: Sheng-Feng Chung
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Publication number: 20250023585Abstract: A wireless communication device for concurrently receiving multiple types of signals and associated methods are provided. The wireless communication device includes at least one low noise amplifier (LNA), a first conversion circuit, a second conversion circuit, a first filter and a second filter. The at least one LNA amplifies an initial signal received by an antenna to generate at least one input signal, wherein the first conversion circuit and the second conversion circuit perform conversion operations according to the at least one input signal to generate a first converted signal and a second converted signal, respectively. More particularly, the first filter performs a filtering operation corresponding to a first-type signal upon the first converted signal, and the second filter performs a filtering operation corresponding to a second-type signal upon the second converted signal.Type: ApplicationFiled: July 9, 2024Publication date: January 16, 2025Applicant: Realtek Semiconductor Corp.Inventors: Ping-Hsuan Tsai, Kuan-Yu Shih, Chia-Jun Chang
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Publication number: 20250024453Abstract: Abstract of Disclosure An uplink scheduling method, for a computer communication network includes determining a ratio of a quantity of transport control protocol (TCP) data and a quantity of an acknowledgement (ACK) of the TCP according to information of a media access control (MAC) layer, system parameters of the MAC layer and transmission data of the computer communication network by a deep learning structure.Type: ApplicationFiled: April 11, 2024Publication date: January 16, 2025Applicant: Realtek Semiconductor Corp.Inventors: Jhe-Yi Lin, Hsien-Chun Huang, Yun-Tai Chen
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Patent number: 12198314Abstract: An image processing method includes: receiving an input image; performing a low-frequency image regulating operation to regulate the local intensity of the image of pixel unit(s) according to low-frequency information of the image of pixel unit(s) of the input image; performing a high-frequency image regulating operation to improve the details of the image of pixel unit(s) according to high-frequency information of the image of pixel unit (s) of the input image; and, generating an output image according to the input image, the low-frequency image regulating operation, and the high-frequency image regulating operation.Type: GrantFiled: April 13, 2022Date of Patent: January 14, 2025Assignee: Realtek Semiconductor Corp.Inventors: Yu-Hsuan Kuan, Tsung-Hsuan Li, Shih-Tse Chen
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Publication number: 20250017110Abstract: A thermoelectric cooling chip including a substrate; a buffer layer on a surface of the substrate; a first etching stop layer on the buffer layer; a dielectric layer on the first etching stop layer; a first conductivity type semiconductor layer in the dielectric layer; a first wire layer in the dielectric layer and directly contacts the sidewall of the first conductivity type semiconductor layer; a second etching stop layer on the first conductivity type semiconductor layer; a second wire layer in the dielectric layer and the second etching stop layer and directly contacts the sidewall of the first conductivity type semiconductor layer; a second conductivity type semiconductor layer on the first conductivity type semiconductor layer; and a third wire layer on the second wire layer, and directly contacts the sidewall of the second conductive type semiconductor layer.Type: ApplicationFiled: May 19, 2024Publication date: January 9, 2025Applicant: Realtek Semiconductor Corp.Inventor: Chih-Yen Su
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Publication number: 20250013383Abstract: A data read-write system includes a receiving terminal, a buffer, a memory and a writing module. The receiving terminal is used for receiving data, and the data includes a plurality of data blocks, and each data block is arranged into a two-dimensional matrix. The buffer includes a plurality of buffer blocks. The writing module includes a twisted block deinterleaving unit, a storage unit and an output unit. The twisted block deinterleaving unit reads each data block to obtain a plurality of first block strings. The storage unit distributes and stores the data blocks in each first block string in each buffer block. The output unit is used for outputting each data block in each buffer block to the memory for storage when the occupied capacity of each buffer block reaches an upper limit of a buffer capacity.Type: ApplicationFiled: January 17, 2024Publication date: January 9, 2025Applicant: REALTEK SEMICONDUCTOR CORP.Inventor: Yi-Lin Shie