Abstract: A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Abstract: A detection system and a detection method are provided. The detection method includes: obtaining first, second and third keypoints of a face by a keypoint acquisition module based on an image containing the face, the keypoint acquisition module obtaining the third keypoint based on a predetermined position on a midline of a human face and the first and the second keypoints based on two paired positions outside the midline; obtaining a vector by a first calculation module based on the first and second keypoints; obtaining a two-variable linear function by a second calculation module based on the vector and the third keypoint; and substituting, by a determination module, the coordinates of the first keypoint and the coordinates of the second keypoint into the two-variable linear function to obtain first and second values, respectively, and determining the state of the face based on the first and second values.

Abstract: A detection system and a detection method are provided. The detection method includes: receiving an image containing a face by an angle acquisition module and obtaining a first angle, a second angle and a third angle of the face based on the image; obtaining a first projection value and a second projection value based on the first angle, the second angle and the third angle by a projection calculation module; and performing by a confidence calculation module: performing an exponentiation calculation on the first projection value based on a first correction value to obtain a third value; performing an exponentiation calculation on the second projection value based on a second correction value to obtain a fourth value; and obtaining a confidence value based on the third value and the fourth value.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Abstract: A USB chip includes positive and negative data pins, first and second transceiver circuits, a switching circuit, and a control circuit. During a high-speed handshake stage, the control circuit controls the switching circuit to be in a second state to disconnect the positive and negative data pins from a first terminal impedance circuit and actuates the second transceiver circuit to transmit a second voltage signal via the positive and negative data pins alternately. During a high-speed transmission stage, the control circuit controls the switching circuit to be in a first state to connect the positive and negative data pins with the first terminal impedance circuit and actuates the first transceiver circuit to transmit a first voltage signal, which has a first voltage level lower than a voltage level of the second voltage signal, via the positive and negative data pins alternately.

Abstract: A reference potential generating circuit includes at least one upper-potential selection switch, at least one lower-potential selection switch, a resistor string and at least one multiplexer. Each upper-potential selection switch receives an upper-voltage signal, and one of the upper-potential selection switches is turned on. Each lower-potential selection switch receives a lower-voltage signal, and one of the lower-potential selection switches is turned on. The resistor string is coupled between the upper-potential selection switch and the lower-potential selection switch. The multiplexer includes a plurality of input ends and an output end. The input ends are coupled to ends of the resistors one to one, and the output end of one of the multiplexers outputs a reference potential signal. A control method for the aforementioned reference potential generating circuit is further provided here.

Abstract: A driving circuit for driving a resonant device includes a voltage sensor, a signal controller, a signal generator and a driver. The voltage sensor, coupled to the resonant device, is configured to detect a back electromotive force (EMF) of the resonant device. The signal controller, coupled to the voltage sensor, is configured to control the length of an operation period of the driving circuit according to the back EMF. The signal generator, coupled to the signal controller, is configured to generate a driving signal corresponding to the length of the operation period. The driver, coupled to the signal generator, is configured to output the driving signal to the resonant device.

Abstract: The present invention provides an image processing method, wherein the image processing method includes the steps of: receiving an image signal, wherein the image signal comprises a frame; performing a motion estimation operation on a plurality of blocks within the frame to generate a plurality of first motion vectors, respectively; scaling down the frame to generate a scaled-down frame; performing the motion estimation operation on a specific block within the scaled-down frame to generate a second motion vector corresponding to the specific block; and determining a plurality of final motion vectors of the plurality of blocks of the frame according to the plurality of first motion vectors and the second motion vector.

Abstract: A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

Abstract: A command transforming method, applied to a command transforming system comprising a first transceiving interface and a second transceiving interface, comprising: receiving at least one command transmitted from a first device via the first transceiving interface; determining a first sequence rule of the first device and a second sequence rule of a second device, wherein the first sequence rule means if the first device is required to process the command in sequence and the second sequence rule means if the second device is required to process the command in sequence; transmitting the command to the second device via the second transceiving interface; processing the command by the second device according to the second sequence rule and transmitting a response corresponding to the command to the second transceiving interface by the second device; and transmitting the response to the first device according to the first sequence rule.

Abstract: A multi-gain stage circuit is arranged to receive an input signal to generate an output signal, and includes a first gain stage, a second gain stage, a gain control circuit, and a calibration circuit. The second gain stage is connected in series with the first gain stage, and the second gain stage generates the output signal. The gain control circuit controls the first gain stage to have a first gain value such that the output signal is regarded as a product of a gain value of the second gain stage and an offset voltage of the second gain stage. The calibration circuit calculates the offset voltage of the second gain stage according to the output signal, and calibrates the second gain stage according to the offset voltage of the second gain stage calculated by the calibration circuit.

Abstract: A clock generating circuit includes a control circuit and a phase interpolator. The control circuit converts an input signal to generate an encoded signal having multiple bits and adjusts arrangement of the bits according to a pointer to generate a control signal having multiple control bits. The phase interpolator includes a first driving circuit, a second driving circuit and an output terminal configured to output an interpolated clock signal. The first driving circuit receives a first clock signal and includes multiple first driving units that are turned on or off to drive the first clock signal in response to multiple first control bits in the control bits. The second driving circuit receives a second clock signal and includes multiple second driving units that are turned on or off to drive the second clock signal in response to multiple second control bits in the control bits.

Abstract: A method for sharing a storage device among multiple processors and an associated electronic device are provided. The method includes: controlling a first processor and a second processor to operate in an access mode and a detection mode, respectively; in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device; in response to a first predetermined condition, controlling the first processor to enter the detection mode from the access mode; in response to a second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission.

Abstract: An apparatus and a method for performing debug control in a chip are provided, wherein the apparatus includes a first counter, a first determination circuit, a second counter and a second determination circuit. The first counter counts a number of execution times of a specific system request in the chip to generate a first counting result, and the first determination circuit generates a first determination result according to the first counting result. The second counter counts a number of cycles of an execution clock to generate a second counting result, and the second determination circuit generates a second determination result according to the second counting result. When the first determination result indicates that the first counting result reaches a first threshold and the second determination result indicates that the second counting result reaches a second threshold, execution of the chip is suspended at a breakpoint state.

Abstract: A data compression method, for compressing at least portion of data of a data group, comprising: defining X sub data groups, wherein each of the sub data groups comprises a portion of the data group; compressing each of the sub data groups via Y compression algorithms, to generate Y compression results for each of the sub data groups, wherein X and Y are positive integers and X is at least 2; selecting a preferred compression algorithm for each of the sub data groups according to corresponding ones of the Y compression results; and compressing the sub data group by the preferred compression algorithm thereof to generate a plurality of compressed data units.

Abstract: A signal processing method for processing a signal received by a receiver device includes: performing a first correlation calculation on the received signal to obtain a first calculation result; performing carrier frequency offset estimation and compensation on the received signal to obtain a first compensated signal; performing a second correlation calculation on the first compensated signal to obtain a second calculation result; performing carrier frequency offset compensation on the first compensated signal to obtain a second compensated signal; determining whether at least one phase of the second compensated signal is correct; and determining whether at least one decoding result of the second compensated signal is correct. The received signal is determined not a signal conforming to a predetermined standard when the at least one phase of the second compensated signal or the at least one decoding result of the second compensated signal is determined incorrect.

Abstract: A debugging management platform and an operating method for the same are provided. In the operating method, the debugging management platform operates a debugging agent service for establishing a debugging channel between a software development platform and a test platform. When receiving debugging packets are issued by the software development platform or the test platform, the debugging agent service analyzes the debugging packets and checks if the debugging packets meet an information security standard. The debugging packets are forwarded to the test platform or the software development platform if the debugging packets meet the information security standard. If the debugging packets do not meet the information security standard, the debugging packets are not forwarded, so as to ensure information security of the debugging packets that are forwarded between different environments.