Patents Assigned to Realtek Semiconductor Corp.
  • Patent number: 12783198
    Abstract: An operation method of an electronic display device includes: receiving multiple data sources; providing a display screen to respectively display the multiple data sources of the multiple data source devices by activating multiple different windows; providing a peripheral control circuit to receive a user control signal from an external peripheral device to transfer the user control signal into the controller circuit; and, controlling the display screen based on the user control signal to control the display screen respectively displaying the multiple data sources through multiple different windows, to respectively and dynamically control and manage the picture positions on the display screen and dynamically controlling the window sizes of the multiple different windows.
    Type: Grant
    Filed: November 28, 2025
    Date of Patent: November 3, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ding-Wei Chen, Yi-Wen Lin
  • Patent number: 12786872
    Abstract: A method of operating a station multi-link device (STA MLD). The STA MLD includes N radio chains, M antennas and a processor. N and M are positive integers, M?N. The processor is coupled to the N radio chains. The method includes the processor setting the STA MLD to a multi-link multi-radio (MLMR) mode, the processor setting each radio chain as performing data transmissions via the M antennas, and the processor setting a power save mode of at least one radio chain to a doze state. The method further includes the processor allocating the M antennas to the N radio chains according to an application scenario, and the processor updating the N power save modes of the N radio chains according to the application scenario.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: November 3, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventor: Hsin-Ta Huang
  • Patent number: 12783205
    Abstract: A method for displaying a casted content on a split window and a circuit system are provided. The circuit system is applied to a display device. When the display device operates under a multi-window display mode, and the method is performed, the circuit system receives an image transmitted from a user device by an image-casting technology. An active region of the image can be obtained through an edge-finding process. The image of the active region can be extracted by cropping an inactive region. The image of the active region can be displayed in one of split windows of the display device after a display ratio of the image is adjusted according to an aspect ratio of the active region.
    Type: Grant
    Filed: March 7, 2025
    Date of Patent: November 3, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Jie Wang
  • Patent number: 12783848
    Abstract: A method for improving a convolutional neural network (CNN) to perform computations is provided. The method includes the following steps: determining a number of a plurality of multipliers to be N and a number of a plurality of adders to be N according to a number of convolution kernels used by a plurality of convolution layers; and in response to an i-th convolutional layer of the convolutional neural network performing a convolution operation and N convolution kernels of the i-th convolutional layer being all in a size of K×1×1, using the N multipliers and the N adders to perform a multiplication operation once and an addition operation once for each of the N convolution kernels of the i-th convolutional layer in one cycle, such that N outputs of the N convolution kernels of the i-th convolutional layer are obtained after K cycles.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 3, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Li-Li Tan, Wen-Tsai Liao
  • Patent number: 12782999
    Abstract: An electronic device and a clock jitter analysis method are provided. The electronic device includes a storage device and a processing device. The processing device is configured to: read timing simulation information and voltage drop information of a plurality of clock paths from the storage device; obtain a maximum voltage drop and a minimum voltage drop of each clock path based on the voltage drop information; perform a first static timing analysis (STA) with the maximum voltage drop based on the timing simulation information, to obtain a first timing report; perform a second STA with the minimum voltage drop based on the timing simulation information, to obtain a second timing report; calculate time information corresponding to each clock path based on the first timing report and the second timing report; and select largest time information of the plurality of pieces of time information as a clock jitter.
    Type: Grant
    Filed: May 5, 2025
    Date of Patent: November 3, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Yu-Lan Lo
  • Patent number: 12786484
    Abstract: A multi-platform live streaming device is provided. The multi-platform live streaming device includes: a user interface service module and a streaming output service module. The user interface service module is configured to control one or more image elements based on a user interface setting, thereby determining screen layouts of a local monitoring video and a live output video respectively. The streaming output service module is configured to encode the live output video to generate live streaming media and streaming the live streaming media simultaneously to multiple live streaming platforms. Specifically, the screen layout of the local monitoring video can differ from that of the live output video.
    Type: Grant
    Filed: August 28, 2024
    Date of Patent: November 3, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Cheng Lin, Jie Wang, Sung-Chen Yang
  • Patent number: 12785823
    Abstract: An impedance transformation circuit and a radio frequency power reliability test system are provided. The impedance transformation circuit can be used in a radio frequency power measurement system. The radio frequency power measurement system includes a signal generator, a buffer, a device under test, an attenuator, and a spectrum analyzer. The impedance transformation circuit includes a plurality of impedance transformers, which correspond to a plurality of impedance points on a reflection coefficient circle of a Smith chart, respectively. In a radio frequency power reliability test, the impedance transformers are alternatively coupled between the device under test and the attenuator in turn, and the spectrum analyzer is configured to measure an output power corresponding to each of the impedance points, such that two of the impedance points respectively corresponding to a maximum output power and a minimum output power are found by the radio frequency power measurement system.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: November 3, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chia-Hsiang Hsu, Chih-Chieh Wang
  • Patent number: 12786651
    Abstract: An audio processing system and an audio processing method are provided. The audio processing system includes a receiving circuit and a processing circuit. The receiving circuit is configured to adjust original extended display capability identification data for generating optimized extended display capability identification data. The audio source device reads the optimized extended display capability identification data. The audio source device responds to the receiving circuit with a first multi-channel signal according to the optimized extended display capability identification data, and a quantity of sound channels of the first multi-channel signal is greater than a maximum quantity of sound channels supported by the audio processing system. The processing circuit is configured to convert the first multi-channel signal into a second multi-channel signal, and a quantity of sound channels of the second multi-channel signal is different from that of the first multi-channel signal.
    Type: Grant
    Filed: December 2, 2024
    Date of Patent: November 3, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chun-Chieh Chan, Hung-Shao Chen, Tzu-Hsin Fan
  • Publication number: 20260342295
    Abstract: The present invention provides a transceiver including a transmitting circuit, wherein the transmitting circuit includes a baseband amplifier, a mixer, a power amplifier and a phase compensation circuit. The baseband amplifier is configured to amplify a baseband signal to generate a baseband transmission signal. The mixer is configured to mix the baseband transmission signal using an oscillation signal to generate a RF transmission signal. The power amplifier is configured to amplify the RF transmission signal to generate an amplified RF transmission signal for transmission to an antenna. The phase compensation circuit is coupled to an output terminal or an input terminal of the baseband amplifier, and configured to compensate for a phase of the baseband transmission signal; or the phase compensation circuit is coupled to an output terminal or an input terminal of the power amplifier, and configured to compensate for a phase of the amplified RF transmission signal.
    Type: Application
    Filed: March 30, 2026
    Publication date: October 29, 2026
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ping-Hsuan Tsai, Chia-Jun Chang
  • Publication number: 20260340770
    Abstract: An image processing system, an image processing method, a non-transitory computer readable recording medium with a stored program, and a non-transitory computer program product, where the image processing method includes: receiving an input image; obtaining a previous mask image of the input image and enlarging the previous mask image to obtain a mask image, where a size of the mask image is the same as a size of the input image; performing a picture quality function on the input image through a picture quality module to obtain a picture quality image; and performing a pixel weight averaging procedure on the input image and the picture quality image based on values of each of a plurality of pixels of the mask image to obtain an output image.
    Type: Application
    Filed: April 3, 2026
    Publication date: October 29, 2026
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Cheng Cheng, Jia-Wei Wu, Yu-An Chang
  • Publication number: 20260330238
    Abstract: A training system, a training method, a predicting system, a predicting method, a computer readable recording medium with a stored program, and a non-transitory computer program product are provided. The training method is executed by a processing module. A module to be trained includes a neural network model and a plurality of parameters. The training method includes executing the following steps: receiving training data, where each piece of training data includes training input data and label data, the training input data includes a stress time, a plurality of element ratios corresponding to a plurality of basic elements, a driving strength, and an operating voltage of one of a plurality of benchmark circuits, and the label data includes a speed degradation ratio; and training the module to be trained based on the training data.
    Type: Application
    Filed: December 30, 2025
    Publication date: October 22, 2026
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chao-Wei Lin, Zhi-Hong Huang
  • Publication number: 20260332116
    Abstract: A receiver circuit includes a first amplifier circuit, a mixer, a second amplifier circuit, a compensation circuit, and a controller circuit. The first amplifier circuit processes a reception signal according to a first gain to generate a first amplification signal. The mixer receives the first amplification signal, and performs a frequency conversion operation upon the first amplification signal according to an oscillation signal to generate a frequency-converted signal. The second amplifier circuit receives the frequency-converted signal, and processes the frequency-converted signal according to a second gain to generate a second amplification signal. The compensation circuit coupled to an output terminal of the first amplifier circuit provides an impedance at the output terminal of the first amplifier circuit.
    Type: Application
    Filed: March 24, 2026
    Publication date: October 22, 2026
    Applicant: Realtek Semiconductor Corp.
    Inventors: I-Ju Chen, Kuan-Yu Shih
  • Publication number: 20260333038
    Abstract: A signal processing system includes a receiving module, a storage module, and a processing module. The receiving module is configured to receive a wireless signal. The wireless signal includes authentication information and training information. The storage module is configured to store a smoothing parameter. The processing module is coupled to the receiving module. The processing module is configured to: (a) obtain the corresponding smoothing parameter from the storage module according to the authentication information; (b) obtain first channel state information by performing channel estimation according to the training information; (c) obtain second channel state information by performing smoothing processing on the first channel state information according to the smoothing parameter; and (d) generate sensing information according to the second channel state information.
    Type: Application
    Filed: April 7, 2026
    Publication date: October 22, 2026
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wen-Yung Lee, Syu-Min Cyu, Hsin-Hong Chou
  • Patent number: 12769914
    Abstract: A margin correction method and a margin correction system for static timing analysis are provided. The margin calibration method includes: measuring dies on a to-be-tested chip with a target circuit to obtain performance data records; obtaining simulation data records for simulating performances of the dies; executing a static timing analysis (STA) tool to obtain timing analysis results; statistically calculating a simulation process corner based on the timing analysis results; obtaining a measurement process corner based on the performance data records; establishing a statistical model that defines a margin as a difference between the measurement process corner and the simulation process corner; substituting the timing analysis results and the measurement process corner into the statistical model and execute a model fitting algorithm, for fitting the statistical model to a target model to obtain the margin; and obtaining calibrated timing analysis results.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: October 20, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Yu-Lan Lo
  • Patent number: 12768941
    Abstract: A processing circuit includes: an estimating circuit, for generating a phase vector according to a phase signal, and for estimating the phase vector to generate an estimated phase matrix; a decomposing circuit, for decomposing the estimated phase matrix to generate an eigenvalue matrix and an eigenvector matrix; a first computing circuit, for performing a long-term average for a plurality of eigenvalues to generate a plurality of long-term eigenvalues; a second computing circuit, for computing a plurality of difference values for the plurality of long-term eigenvalues, and for determining an index corresponding to a difference value of the plurality of difference values; a spectrum generation circuit, for generating a pseudo spectrum according to the index, a plurality of eigenvectors and a steering vector; and a determining circuit, for determining at least one peak of the pseudo spectrum and at least one parameter corresponding to the at least one peak.
    Type: Grant
    Filed: October 8, 2024
    Date of Patent: October 20, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Patent number: 12772856
    Abstract: A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: October 20, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yung-Chung Chen
  • Patent number: 12771657
    Abstract: A signal compensation device includes a first receiving circuit, a second receiving circuit, a first buffer, a second buffer, a third buffer, and a processing circuit. The first receiving circuit receives a first video signal from a first video source. The second receiving circuit receives a second video signal from a second video source, wherein both the first video signal and the second video signal correspond to a same program. The first buffer stores a first transport stream (TS) packet group corresponding to the first video signal. The second buffer stores a second TS packet group corresponding to the second video signal. The processing circuit dynamically stores a first TS packet of the first TS packet group or a second TS packet of the second TS packet group to the third buffer according to a predetermined source in response to TS packet status.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: October 20, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chun-Yi Chen
  • Publication number: 20260322361
    Abstract: A relaxation oscillator and a method for generating at least one oscillation signal in the relaxation oscillator are provided. The relaxation oscillator includes a capacitor, a resistor, an inverting amplifier and a first logic inverter, where a first terminal of the resistor is coupled to a first terminal of the capacitor. The inverting amplifier is configured to generate a first digital signal according to an analog signal on the first terminal of the capacitor, and the first logic inverter is configured to generate a second digital signal according to the first digital signal, where a second terminal of the resistor is configured to pull up or pull down the analog signal according to the first digital signal, and a second terminal of the capacitor is configured to receive the second digital signal.
    Type: Application
    Filed: April 14, 2026
    Publication date: October 15, 2026
    Applicant: Realtek Semiconductor Corp.
    Inventor: Yu-Hsien Li
  • Patent number: 12764777
    Abstract: A multi-link transmission device includes a first transmission module, a second transmission module, an analysis module and a multi-link control module. The first transmission module transmits each packet in the first transmission module via a first link, and transmits a first transmission condition for each pack transmission for the first transmission module. The second transmission module transmits each packet in the second transmission module via a second link, and transmits a second transmission condition for each pack transmission for the second transmission module. The analysis module computes a ratio of packet consumption rates of the first transmission module and the second transmission module according to the first transmission condition and the second transmission condition. The multi-link control module dispatches a packet to the first transmission module or the second transmission module according to at least the ratio of the packet consumption rates.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: October 13, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventor: Cheng-Hsuan Wu
  • Patent number: D1153065
    Type: Grant
    Filed: April 30, 2024
    Date of Patent: October 13, 2026
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: An-Ming Lee, Bo-Kai Huang, Wu-Chih Lin, Yueh-Hsing Huang