Abstract: A method for matching a color temperature of a display and a system thereof are provided. The system adopts a first color analyzer for obtaining a first regional color value for a specific area of the display, and a second color analyzer for obtaining a global color value for a whole area and a second regional color value for the specific area. While obtaining a difference between the first and second regional color values and another difference between the global color value and the second regional color value, a sum of the differences is calculated. The sum of differences and a global color target value obtained in an offline mode are referred to adjust a correction target for the specific area of the display. A new correction target can be obtained for providing display parameters of colors that are applied to the whole area of the display.

Abstract: A motion detection method includes acquiring a raw image, detecting a motion object image according to the raw image by using a motion detector, cropping the raw image to generate a sub-image according to the motion object image, and inputting the sub-image to a processor for determining if a motion object of the sub-image matches with a detection category. The processor includes a neural network. The shape of the sub-image is a polygonal shape.

Abstract: A wireless MESH network includes multiple low-power nodes. When serving as a data receiving node or a data relay node, each low-power node is configured to listen to data transmission at intervals.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.

Abstract: A variable gain amplifier device includes a variable gain amplifier circuitry and a control voltage generating circuitry. The variable gain amplifier circuitry is configured to amplify input signals to generate output signals, wherein the variable gain amplifier circuitry includes a gain setting circuit that is configured to set a gain of the variable gain amplifier circuitry according to a control voltage. The control voltage generation circuitry is configured to simulate at least one circuit portion of the variable gain amplifier circuitry, in order to generate the control voltage according to the input signals and a setting voltage.

Abstract: This invention discloses a method for controlling a wireless communication device to reduce the number of retry times of data packets during transmission. The method includes steps of: using a first packet length to generate and transmit data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; and using a second packet length smaller than said first packet length to generate and transmit data packets when said result is greater than a predetermined value.

Abstract: An isolation estimation system includes a transmitter device, a first receiver device, a second receiver device, and a processor circuit. The transmitter device adopts a first communication technology. The transmitter device is configured to transmit a transmitting signal to the first receiving device. The second receiver device is configured to acquire a leakage signal power spectral density of a leakage signal corresponding to the transmitting signal. The second receiver device adopts a second communication technology. A bandwidth of the second communication technology is narrower than a bandwidth of the first communication technology, and the second communication technology supports a frequency hopping process. The processor circuit is configured to calculate isolation according to a signal-in-air power spectral density of the transmitting signal and the leakage signal power spectral density. The isolation is for determining whether to adjust the transmitter device.

Abstract: The application discloses a polar system and a delay difference calibration method. The polar system includes: a calibration signal generation unit, a CORDIC, a delay difference generation unit, a transmission unit, a receiving unit, a Fourier transformer and a calibration unit. The receiving unit is configured to receive a transmission signal from the transmission unit. The Fourier transformer is configured to compute a power of a receiving signal at a specific frequency. The calibration unit is configured to control the delay difference generation unit and determine a delay difference calibration value in a calibration mode.

Abstract: The application discloses a transmitter with self-interference calibration ability, including: a signal generation unit for generating a signal; a CORDIC for generating an amplitude modulation signal and a phase modulation signal according to the signal; phase processing unit, for generating a frequency signal according to the phase modulation signal; a DPLL, including: a DCO, self-interference calibration unit, for generating phase compensation according to the signal, a phase difference and a reference clock; and a DCO control generation unit; and an output unit, for generating an output signal according to the amplitude modulation signal and a DCO output signal.

Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Abstract: A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.

Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.

Abstract: A signal processing method in a digital-domain includes: adding a random number sequence signal into a time-domain input signal to generate a time-domain processed input signal; performing a Fourier transform operation upon the time-domain processed input signal to generate a frequency-domain processed input signal; performing an equalizer operation upon the frequency-domain processed input signal to generate a frequency-domain output signal according to coefficients of the equalizer operation; performing an inverse Fourier transform operation upon the frequency-domain output signal to generate a time-domain output signal; generating a decision output signal and generating a time-domain error signal according to the time-domain output signal; and determining the coefficients according to the time-domain error signal and the frequency-domain processed input signal.

Abstract: A device for sound localization includes a spatial feature generator, a voice detector, an angle selector, and an angle retriever. The spatial feature generator generates M spatial feature signals according to signals of N microphones of a microphone array. The voice detector generates at least one voice detection signal according to at least one of the signals of the N microphones. The angle selector outputs a candidate angle signal according to the M spatial feature signals to indicate a candidate direction of sound. The angle retriever generates a sound detection result according to the M spatial feature signals to indicate whether any sound source exists, and then outputs an estimated angle signal indicative of a direction of sound according to the sound detection result, the at least one voice detection signal, and the candidate angle signal.

Abstract: Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.

Abstract: A cache and a method for managing a cache are provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit and is configured to find a storage space in the storage circuit and write the data to the storage space.

Abstract: The present disclosure discloses a memory write operation apparatus to perform write operation on a selected memory unit coupled to two bit lines that includes a coupling capacitor, a charge sharing circuit, a write operation driving circuit, a charging circuit and a negative voltage coupling circuit. The charge sharing circuit electrically couples a first terminal of the coupling capacitor and a first bit line to receive charges therefrom to perform charging. The negative voltage coupling circuit electrically couples the first terminal of the coupling capacitor to a ground terminal during a negative voltage generation time period such that a second terminal of the coupling capacitor couples a negative voltage to the first bit line to perform write operation.

Abstract: An amplifier device includes an alternate current (AC) coupling circuit, an amplifier circuit, and a first bias circuit. The amplifier circuit is configured to amplify an input signal to generate an output signal, in which the amplifier circuit includes a first input terminal, and the first input terminal receives the input signal via the AC coupling circuit. The first bias circuit is configured to apply a first bias voltage to the first input terminal according to one of the output signal and a first voltage, such that the amplifier circuit amplifies the input signal to output the output signal.

Abstract: An image debanding method includes selecting a first and a second comparison pixel from a plurality of adjacent pixels within a preset pixel distance range in a straight pixel direction according to each of the plurality of adjacent pixels and the to-be-compensated pixel; calculating a first compensation value according to a first difference between pre-debanding color values of the first comparison pixel and the to-be-compensated pixel, a first pixel distance between the first comparison pixel and the to-be-compensated pixel, and the preset pixel distance range; calculating a second compensation value according to a second difference between the pre-debanding color values of the second comparison pixel and the to-be-compensated pixel, a second pixel distance between the second comparison pixel and the to-be-compensated pixel, and the preset pixel distance range; and calculating a post-debanding color component value of the to-be-compensated pixel.