Abstract: A gain modulation circuit includes a load circuit, a differential circuit, a current source, a resistor, a first transistor, and a detector circuit. The load circuit is configured to receive a supply voltage. The differential circuit is coupled to the load circuit. The differential circuit and the load circuit are configured to generate a pair of output voltages according to a pair of input voltages and the supply voltage. The current source is coupled to the differential circuit. The resistor is coupled to the differential circuit and the current source. The first transistor is coupled to the differential circuit. The detector circuit is configured to generate a detection signal according to the pair of input voltages. A turned-on degree of the first transistor is adjusted based on the detection signal, to adjust a linear region of the gain modulation circuit.

Abstract: An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.

Abstract: The present invention provides a transceiver. The transistor is coupled to a transmission line. The transceiver includes a variable resistor set, a transmitter module, a receiver module, and a digital signal processor. The transmitter module has an output terminal coupled to the variable resistor set and the transmission line. The transmitter module includes a first digital-to-analog converter configured to output an emission current. The receiver module has an input terminal coupled to the transmitter module and the transmission line. When the emission current is fed into the transmission line, a far-end echo is fed into the receiver module. An amplitude of the far-end echo is associated with a resistance value of the transmission line. The digital signal processor adjusts a current value of the emission current from a first default current value to a second default current value based on the amplitude of the far-end echo.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A satellite signal receiving circuit includes an oscillator, two mixers, two phase shifters, two low-pass filters, two phase operation circuits, and a bandpass filter. When the frequency of the oscillator is between the center frequencies of the Global Orbiting Navigation Satellite System (GLONASS) and the GPS or the Galileo system, the GLONASS and GPS/Galileo satellite baseband signals are obtained through phase addition and subtraction performed by the phase operation circuits, while the BeiDou Navigation Satellite System (BDS) baseband signal is obtained through the bandpass filter. When the frequency of the oscillator is between the center frequencies of the BDS and the GPS or the Galileo system, the BDS and GPS/Galileo satellite baseband signals are obtained through phase addition and subtraction performed by the phase operation circuits, while the GLONASS satellite baseband signal is obtained through the bandpass filter.

Abstract: A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit. The host accesses data according to the communications protocols of USB. The USB interface adaptor accesses data through a first port according to the communications protocols of USB, and accesses data through a second port according to the communications protocols of FIFO. The FIFO interface adaptor accesses data through a third port coupled to the second port according to the communications protocols of FIFO, and accesses data through a fourth port according to the communications protocols of a specific type of bus. The bus bridge circuit transmits the data received from the fourth port to a functional circuit according to the communications protocols of the specific type of bus.

Abstract: A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.

Abstract: A method and apparatus for performing spatial reuse (SR) enhancement in a multiple-station environment are provided.

Abstract: The present disclosure provides a data shifting operation apparatus having multiple operation modes that includes a preprocessing circuit, a first and a second shifting circuits and a multiplexer. The preprocessing circuit stores an input data group, having a data amount equal to a desired data amount M, to an under-operation data group, having the data amount equal to a maximum usage data amount N, from a most significant bit, and receives a shift amount S to calculate a total shift amount. The first and the second shifting circuits respectively cyclically shift the under-operation data group for the shift amount and the total shift amount to generate a first and a second shifted data groups. The multiplexer selects S data from the most significant bit of the second shifted data group and (M?S) data from the (N?S)-th bit of the first shifted data group to output a final shifted data group.

Abstract: An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Abstract: A wireless mesh network includes multiple low-power nodes. When functioning as a data receiving node or a data relay node, each low-power node is used to monitor data transmission at intervals. Each node performs time synchronization based on an SFN and an H-SFN of a base NB-IoT cell. At least one of the multiple low-power nodes is located in the base NB-IoT cell.

Abstract: A communication apparatus having power saving mode includes memory circuit unit and DMA module. The memory circuit unit is used for storing instruction and data information to be executed by microcontroller (or control circuit) of communication apparatus, and the DMA module is used to backup the instruction and data information and store such information into a memory of an electronic device when the communication apparatus receives a broadcast synchronization signal periodically sent from another communication device. During the power saving mode, the memory circuit unit is powered down. When leaving the power saving mode, the memory circuit unit is powered on, and the DMA module retrieves the instruction and data information from the memory of the electronic device and write such information into the memory circuit unit.

Abstract: An output power linearization method, suitable for a calibration system, includes the following operations: providing an instruction signal, which corresponding to a currently ideal output power among multiple ideal output powers, to an emission module of the calibration system so that the emission module outputs a radio frequency (RF) signal with a practical output power according to the instruction signal; obtaining a feedback signal, by a feedback circuit of the calibration system, from an output terminal of the emission module, and calculating a feedback output power from the feedback signal; calculating an output difference between the currently ideal output power and the feedback output power; if an absolute value of the output difference is larger than an absolute value of a feedback error of the feedback circuit, adjusting a present gain of the emission module so that the practical output power approaches the currently ideal output power.

Abstract: Circuitry for detecting an audio standard of a sound intermediate frequency signal includes an intermediate frequency to baseband circuit, a detection circuit and a demodulator/decoder. The intermediate frequency to baseband circuit is configured to process the sound intermediate frequency signal to generate a main tone and a sub-tone. The detection circuit is configured to determine if the sound intermediate frequency signal belongs to a first standard or a second standard according to if the sub-tone has a pilot signal or a digital frame, to generate a detection result. The demodulator/decoder is configured to demodulate/decode at least the main tone to generate an output audio signal.

Abstract: A method for automatically upgrading firmware over the air and a wireless node are provided. The method is applied to a wireless local area network including a plurality of wireless nodes. The method includes: broadcasting, by the wireless node, firmware information, and maintaining a connectable state; scanning, by each of the wireless nodes, other wireless nodes, where when the wireless node scans another wireless node with an old version of firmware information, the scanning wireless node serves as a master wireless node, and the another scanned wireless node serves as a slave wireless node; connecting, by the master wireless node, to the slave wireless node, and sending an upgrade instruction to the slave wireless node; performing, by the slave wireless node, a firmware upgrade according to the upgrade instruction to update to a new version of firmware; and disconnecting the master wireless node from the slave wireless node.

Abstract: An image processing circuit includes a receiving circuit, a feature fetching module and a decision circuit. In the operations of the image processing circuit, the receiving circuit is configured to receive image data. The feature fetching module is configured to use a multi-topological-convolutional network to fetch the features of the image data, to generate a plurality of image features determined by the characteristics and weights of the convolution filter, where the image features may be smooth features or edge features. In the present invention, the convolution filters used by the feature fetching module are not limited by a square convention filter, and the convolution filters may include the multiple topological convolutional network having non-square convolution filters. By using the multiple topological convolutional network of the present invention, the feature fetching module can fetch the rich image features for identifying the contents of the image data.

Abstract: A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.

Abstract: A transmitter device includes a transmitter including a first oscillator circuitry, a signal processing circuitry, and a calibration circuitry, and a second oscillator circuitry. The first oscillator circuitry is configured to output a first oscillating signal. The signal processing circuitry is configured to mix calibration signals according to the first oscillating signal, in order to emit a first output signal. The calibration circuitry is configured to detect a power of the first output signal to generate coefficients, and generate the calibration signals according to the coefficients, an in-phase data signal, and a quadrature data signal. The second oscillator circuitry is disposed adjacent to the transmitter, and is configured to output a second oscillating signal. The calibration signals are configured to reduce a pulling generated by both of the first output signal and the second oscillating signal to the first oscillator circuitry.

Abstract: A method of determining CCA (clear channel assessment) policy, applied in a communication system including multiple devices, is provided. The method includes the following steps: the devices broadcasting multiple policy indications, in which the devices include a coordinating device, multiple neighboring devices and multiple local client devices, the local client devices associate with the coordinating device to form a network, and the neighboring devices operate within at least one neighboring network; the coordinating device obtaining multiple neighboring policy indications from multiple neighboring frames transmitted by the neighboring devices; and the coordinating device determining whether to change a coordinating policy indication corresponding to the coordinating device according to the neighboring policy indications. A policy indication of a device indicates a policy among multiple CCA policies.

Abstract: A method for performing detection control of a write protection function of a memory device, an associated control chip, and an associated electronic device are provided. The method includes: detecting whether the memory device supports a first protocol to generate an interface detection result; detecting whether a write protection switch of the memory device is turned on to generate a write protection detection result; and according to the interface detection result and the write protection detection result, selectively initializing a transmission interface of a control chip as a first transmission interface conforming to the first protocol or a second transmission interface, to allow a host device to access the memory device through the control chip, wherein the first transmission interface corresponds to a first configuration of the control chip, and the second transmission interface corresponds to a second configuration of the control chip.