Patents Assigned to Realtek Semiconductor
  • Publication number: 20210067106
    Abstract: An audio device is adapted to receive and process a digital audio signal and output an analog audio signal. The audio device includes an adder, a digital-to-analog conversion circuit, an amplifying circuit, a voltage detecting circuit and an offset compensating circuit. The voltage detecting circuit detects a supply voltage received by the amplifying circuit. The offset compensating circuit generates a DC offset compensation value according to the supply voltage. The adder adds the digital audio signal and the DC offset compensation value to output an added signal. The digital-to-analog conversion circuit converts the added signal into a converted analog audio signal. The amplifying circuit amplifies the converted analog signal to output an amplified analog signal. Accordingly, the audio device can reduce pop noise caused by a DC offset.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 4, 2021
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shih-Hsin Lin, Che-Hung Lin, Yi-Chang Tu
  • Patent number: 10937120
    Abstract: A video processing system includes a main chip and a processing chip. The main chip receives first data. The processing chip is coupled to the main chip, and receives second data and to perform a video processing on at least one of the first data transmitted from the main chip and the second data, in order to drive a display panel. First video carried on the first data or second video on the second data has a first resolution, and the first resolution is at least 8K ultra high definition.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Shu Chang, Cheng-Hsin Chang, Hsu-Jung Tung, Chun-Hsing Hsieh, Sen-Huang Tang
  • Patent number: 10938394
    Abstract: A motor driving device includes a first hysteresis comparator, a second hysteresis comparator, a logic circuit, a control unit, and an inverter circuit. The logic circuit receives a start signal or a start completion signal to output the first output signal as a commutation signal according to the start signal, or to output the second output signal as the commutation signal according to the start completion signal, clamps the second output signal by the first output signal, stops outputting the commutation signal after the potential state of the commutation signal is changed, and unclamps the second output signal with the first output signal and outputs the commutation signal in response to a difference voltage between the first input signal and the second input signal being greater than a positive value of the first hysteresis voltage or less than a negative value of the first hysteresis voltage.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chien-Wen Chen
  • Patent number: 10939221
    Abstract: An audio processing method and an audio processing system are provided. In the audio processing method, an audio signal is first provided. Then, plural predetermined categories are provided. Then, a classification step is performed on the audio signal according to the predetermined categories. Thereafter, a transform step is performed on the audio signal to convert the audio signal into a frequency domain. Then, a panning step and a summing step are performed on amplitude signals of the audio signal to obtain a total amplitude signal. Thereafter, a separation step and a summing step are performed on phase signals of the audio signal to obtain a total phase signal. Then, an inverse transform step is performed on the total amplitude signal and the total phase signal to obtain an optimized audio signal in a time domain.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Teng-Hsiang Yu
  • Patent number: 10936784
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10938606
    Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yao-Chia Liu, Bo-Yu Chen
  • Patent number: 10938618
    Abstract: Disclosed is a device capable of compensating for amplitude-modulation to phase-modulation distortion. The device includes a transmitter and a controller. The transmitter includes an amplifier circuit, a phase-shift adjustment circuit, and an output circuit. The amplifier circuit is configured to output an amplified signal according to an input signal. The phase-shift adjustment circuit, set between the amplifier circuit and the output circuit, includes at least one of an adjustable capacitor and an adjustable inductor and is configured to adjust the phase shift of the amplified signal according to a control signal. The output circuit is configured to output an output signal according to the amplified signal. The controller is configured to generate the control signal according to the input signal, in which the control signal varies with the input signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Wen-Shan Wang
  • Patent number: 10938438
    Abstract: Disclosed is a radio-frequency (RF) circuit capable of performing an RF characteristic test in a test mode. The RF circuit includes: a test signal generator generating a test signal; an RF receiver, coupled to the test signal generator, transmitting the test signal and thereby generating a receiver analog signal; a coupling circuit transmitting the receiver analog signal to an RF transmitter in the test mode; the RF transmitter transmitting the receiver analog signal and thereby generating a transmitter analog signal; a test result generator, coupled between the RF transmitter and a test result output terminal, including a signal converter for generating a converted signal according to the transmitter analog signal in the test mode, wherein the output signal at the test result output terminal is the converted signal or originated therefrom and relates to the result of the RF characteristic test.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ka-Un Chan, Chih-Lung Chen, Chia-Jun Chang, Po-Chih Wang
  • Patent number: 10931101
    Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Jian-Ru Lin, Liang-Huan Lei, Cheng-Pang Chan
  • Patent number: 10928850
    Abstract: A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Huan-Wen Chen, Po-Hsien Wu, Li-Yu Chen
  • Patent number: 10931787
    Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Kuo Hwang, Jui-Chang Tsao
  • Patent number: 10931436
    Abstract: A detector circuit incudes a calculator circuit and a comparator circuit. The calculator circuit is configured to generate a plurality of first calculation values according to a plurality of first calculation symbols of a Pseudo-Noise Sequence and a plurality of second calculation symbols of a received signal, and generate a second calculation value according to the first calculation values. If a sign of a symbol of the Pseudo-Noise Sequence is the same to a sign of an adjacent symbol, the symbol is one of the first calculation symbols, and the second calculation symbols are corresponding to the first calculation symbols respectively. The comparator circuit is configured to generate a comparison result according to the second calculation value and a threshold value. The comparison result is configured for determining whether the detector circuit correctly receives the Pseudo-Noise Sequence.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shun-Sheng Wang, Ta-Chin Tseng, Tseng-Kuei Lin, Zong-Cheng Wu
  • Patent number: 10930137
    Abstract: An event alarm device includes a sensor, a notification unit, a MESH communication unit, an NB-IoT communication unit, and an MCU. The NB-IoT communication unit is configured to upload the data measured by the sensor. The MCU is configured to detect a specific event according to the data measured by the sensor. When detecting the specific event, the MCU is configured to instruct the notification unit to emit an on-site alarm, instruct the NB-IoT communication unit to send a first warning signal, and instruct the MESH communication unit to send a second warning signal.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventor: Zaiqiang Sun
  • Patent number: 10930024
    Abstract: A color adjustment system includes a memory and a processor. The memory stores instructions. The processor is configured to access the instructions to perform the following: accessing an image; providing a control interface having control points distributed thereon, and the plurality of control points defines a plurality of areas on a color plane; in response to one of the control points being moved from a first location to a second location on the color plane, selecting adjusting areas adjacent to the first location, in order to redefine an original chroma in the adjusting areas to an adjusted chroma; and determining whether pixels of the image match the original chroma in the adjusting areas, and displaying the pixels with the adjusted chroma if the pixels are matched to the original chroma.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shu-Mi Chen, Wen-Tsung Huang, Kai Liu
  • Patent number: 10922791
    Abstract: An image processing method includes: receiving a currently-input image frame and a previously-output image frame; comparing multiple first pixels corresponding to coordinates of the currently-input image frame with multiple second pixels corresponding to coordinates of the previously-output image frame, and obtaining multiple corresponding differences; obtaining multiple dynamic parameter values based on the differences and a dynamic parameter table; obtaining multiple boundary retention values based on the dynamic parameter values and a boundary operator; and obtaining multiple currently-output pixels based on the first pixels, the second pixels, and the boundary retention values. An image processing apparatus performs the image processing method, to increase accuracy of identifying a boundary adjoining a motion region and a non-motion region, and to remove an artifact of the boundary.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 16, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Ming-Ta Lin
  • Patent number: 10922792
    Abstract: An image adjustment method includes: sequentially processing a plurality of pixels in at least one frame, wherein a pixel under processing is a current pixel, the current pixel and multiple adjacent pixels form a current block, and each current block is performed with following operations: reading a grayscale value of each pixel in the current block; determining a region grayscale value and a region variance of the current block according to the grayscale values of the pixels; generating a variance adjustment parameter via a variance adjustment function, wherein the region grayscale value is a variable of the variance adjustment function; generating an adjusted region variance according to the variance adjustment parameter and the region variance; and comparing the adjusted region variance with a variance threshold to determine whether to perform a noise suppression operation on the current pixel.
    Type: Grant
    Filed: January 1, 2020
    Date of Patent: February 16, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Zhong-Yi Qiu, Wen-Tsung Huang, Kai Liu
  • Patent number: 10924061
    Abstract: A crystal oscillator includes an inverter configured to receive a first voltage at a first node and output a second voltage at a second node, a stacked-diode feedback network inserted between the first node and the second node, a waveform shaper configured to couple the second node to a third node in accordance with the first voltage, a crystal inserted between a fourth node and a fifth node, wherein the fourth node is coupled to the third node, and the fifth node is coupled to the first node, a first shunt capacitor inserted between the fourth node and a ground node, and a second shunt capacitor inserted between the fifth node to and the ground node.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: February 16, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Publication number: 20210043155
    Abstract: This application provides an over-drive compensation method and a device thereof. The over-drive compensation method includes: receiving three primary color information of a current frame, and converting the three primary color information into color space information with luminance, to obtain a current luminance information from the color space information; buffering and storing the current luminance information in a buffer memory and outputting, by the buffer memory, previous luminance information of a previous frame; and generating a luminance over-drive gain value according to the current luminance information and previous luminance information; converting the luminance over-drive gain value into a three primary color over-drive gain value; and generating, according to the three primary color information and the three primary color over-drive gain values, corresponding over-drive compensated values for output to over-drive the liquid crystal display panel.
    Type: Application
    Filed: March 4, 2020
    Publication date: February 11, 2021
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Li-Ang CHEN
  • Patent number: 10914785
    Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 9, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chihtung Chen, Hsing-Han Tseng, Yi-Te Yeh, Yung-Jen Chen, Te-Ming Kuo
  • Patent number: 10916278
    Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen, Fu-Chin Tsai, Shih-Han Lin, Min-Han Tsai