Abstract: A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

Abstract: A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample-and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: A circuit includes a first TSCP (tri-state charge pump) configured to receive a first phase and a third phase of a six-phase signal; a second TSCP configured to receive a second phase and a fourth phase of the six-phase signal; a third TSCP configured to receive a third phase and a fifth phase of the six-phase signal; a fourth TSCP configured to receive a fourth phase and a sixth phase, a fifth TSCP configured to receive the fifth phase and the first phase, and a sixth TSCP configured to receive the sixth phase and the second phase of the six-phase signal. The first, third, and fifth TSCPs output currents to a first output node and the second, fourth, and sixth TSCPs output currents to a second output node. A load is placed across the first output node and the second output node.

Abstract: A method for dynamically limiting a memory bandwidth of a graphics processing unit (GPU) is applicable to a bandwidth-limited system. The bandwidth-limited system includes an audio/video decoder and a GPU. The method includes detecting a plurality of decoding times of a plurality of frames of an audio/video decoded by an audio/video decoder, and adjusting a max grant amount of a memory bandwidth of a GPU according to the plurality of decoding times of the plurality of frames and a target time. Therefore, in the case where the total memory bandwidth is limited, the memory bandwidth of the GPU is limited by the performance of the corresponding audio/video decoder such that, during audio/video playback, the effect of audio/video playback can be prevented from being affected and at the same time a better graphical user interface can be provided.

Abstract: A method includes generating a reference clock using a crystal oscillator; generating a first clock based on the reference clock using a clock multiplier unit, in which a frequency of the first clock is higher than a frequency of the reference clock by a clock multiplier factor; generating a second lock based on the first clock using a frequency multiplying circuit in accordance with a frequency multiplying signal, in which a frequency of the second clock is higher than the frequency of the first clock by a factor that is equal to either five fourths or three halves, depending on whether the frequency multiplying signal is in a first state or in a second state; dividing down the second clock by a factor of two to generate a first LO (local oscillator) signal; dividing down the first LO signal by a factor of two to generate a second LO signal.

Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.

Abstract: An audio enhancement device including an audio-calculating module, a ratio-calculating module, a minimum-tracking module, a weighting-calculating module and a mixing module is provided. The audio-calculating module calculates a mid signal and a side signal according to a sum and a difference of an input first channel signal and an input second channel signal. The ratio-calculating module calculates a side-mid ratio of the side signal relative to the mid signal. The minimum-tracking module tracks a side-mid ratio minimum. The weighting-generating module determines a first and a second weighting values according to the side-mid ratio minimum. The mixing module weights the mid signal and the side signal based on the first and the second weighting values respectively and adjusts the input first channel signal and the input second channel signal accordingly to generate an enhanced first channel signal and an enhanced second channel signal.

Abstract: A wireless communication system includes an access point and at least one station, wherein when the access point operates in a setup mode, both the access point and station confirm a specific time slot for transmitting a packet from the station to the access point; and when the access point operates in a data mode following the setup mode, the station directly uses the specific time slot determined in the setup mode to transmit the packet to the access point.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: An image processing method, applied to a device including a sensor and a processor connected to the sensor, the sensor including a plurality of pixels, in which each of the pixels senses three primary colors and an infrared ray of an image, the processor executing the method including: calculating a real response value of the infrared ray without a crosstalk interference from the three primary colors according to the crosstalk interference from the three primary colors to the infrared ray; calculating real response values of the three primary colors without a crosstalk interference from the infrared ray according to the crosstalk interference of the real response value from the infrared ray to the three primary colors; and increasing a brightness of the image according to a brightness of the real response value of the infrared ray and the real response values of the three primary colors.

Abstract: A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.

Abstract: The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.

Abstract: A transmitter with compensating mechanism of pulling effect includes an output unit and a correction unit. The output unit mixes a first correction signal and a second correction signal according to an oscillating signal to generate a modulated signal, and to amplify the modulated signal to generate a first output signal. The correction unit analyzes the power of the first output signal to generate a first coefficient and a second coefficient, and generate the first correction signal and the second correction signal according to the first coefficient, the second coefficient, an in-phase data signal, and a quadrature data signal.

Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.

Abstract: A network including a current-mode transmitter configured to receive a first voltage and output a first current to a first node in accordance with a first control signal. A transmission line is configured to conduct a signal transmission between the first node and a second node, wherein the transmission line comprises an internal tapping point at a third node. A first transimpedance amplifier is configured to receive a second current from the second node and output a second voltage in accordance with a second control signal. Further; a second transimpedance amplifier is configured to receive a third current from the third node and output a third voltage in accordance with a third control signal.

Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

Abstract: A method of cell search for a mobile device in a wireless communication system is provided. The method comprises performing a reception timing detection procedure, to obtain at least a possible reception time for a primary synchronization signal (PSS), performing a PSS hypothesis procedure, to generate three frequency-domain PSS sequences according to three root indexes each corresponding to a physical layer identity, and performing a secondary synchronization signal (SSS) coherent detection procedure, to calculate a SSS sequence according to each of the at least a possible reception time with the three frequency-domain PSS sequences, to obtain a physical layer cell identity group corresponding to the SSS sequence.

Abstract: The present disclosure illustrates an electronic device with wake on voice function and an operating method thereof. The electronic device detects an audio signal in analog form by an additional pre-signal detector, and the pre-signal detector wakes up an analog-to-digital converter and a human voice detector when the audio signal in analog form is determined to satisfy a predetermined condition. When a host system of the electronic device enters into a sleep mode from an operation mode, the analog-to-digital converter and the human voice detector enter into a sleep mode together.

Abstract: The present invention discloses a DDR4 memory I/O driver including a pre-driver, a pull-up circuit and a pull-down circuit. The pre-driver is coupled between a first high voltage terminal and a low voltage terminal to provide a first and a second pre-driving signals. The pull-up circuit includes: a driving PMOS transistor coupled between a second high voltage terminal and a pull-up resistor, that is coupled to an output pad, to operate according to the first pre-driving signal, in which the second high voltage terminal's voltage is not higher than the first high voltage terminal's voltage. The pull-down circuit includes: a driving NMOS transistor coupled between the low voltage terminal and a cascode NMOS transistor to operate according to the second pre-driving signal; and the cascode NMOS transistor coupled between the driving NMOS transistor and a pull-down resistor, that is coupled to the output pad, to operate according to a bias.