Abstract: A current sense circuit is provided. The circuit includes a current mirror circuit QN1, QN2, and diode-connected QP1, QP2, QP3, and QP4 with their bases connected together, stacking such that the diode-connected side (QN1, QP1, QP3) aligns and connecting the emitter of QP2 to the collector of QP4. Furthermore, the gates of MP1 and MP2 are connected to the collector of QN2 and QP2, respectively. Additionally, the source of MP1 is connected to the drain of MP3 via the source of MP2 and also connected to the source of a Sense MOS. Moreover, the emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source (OUT terminal) of a Main MOS. Furthermore, the gates of MP3 and MP4 are connected to the emitters of QN1 and QN2.

Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.

Abstract: Systems and methods for evaluating a set of bounding boxes in a blended image are described. A system can include an integrated circuit configured to obtain expected bounding box data. The expected bounding box data can be based on coordinates data of an image. The integrated circuit can determine target coordinates based on the expected bounding box data. The integrated circuit can receive a blended image including a set of objects and a set of bounding boxes. The integrated circuit can extract pixel values located at the target coordinates in the blended image. The integrated circuit can identify an error relating to the set of bounding boxes based on the extracted pixel values and the expected bounding box data.

Abstract: According to an aspect, a transceiver comprises a transmitter section having a first PLL (phased locked loop) providing a first reference signal to the transmitter section, a receiver section having a second PLL providing a second reference signal to the receiver section, a coupler coupling the second PLL to the transmitter section when the transceiver is operative in a test mode measuring a first noise component introduced by the first PLL. The first reference signal is coupled to the receiver section internally within the transceiver as a local reference signal to the receiver section both in the test mode and a functional mode.

Abstract: Systems and methods for sensing and processing biosignals are described. An example system can include a first device configured to sense at least one biosignal and a second device. The second device can receive the at least one biosignal from the first device. The second device can receive power via a first wireless interface. The second device can charge a rechargeable battery using the received power. The second device can receive a signal via the first wireless interface, wherein the signal encodes credentials of a user. The second device can demodulate the signal to decode the user credentials. The second device can authenticate the user credentials. The second device can, in response to authentication of the user credentials, communicate the at least one biosignal to a user device via a second wireless interface.

Abstract: A filter circuit for use with a system configured to be coupled with an electrical load, the filter circuit comprising a first filter, wherein the first filter is configured to receive a first voltage and provide an output voltage, the output voltage being the first voltage after filtering by the first filter, and the filter circuit is configured to adjust the bandwidth of the first filter in response to a load transient.

Abstract: A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.

Abstract: A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

Abstract: A power converter controller is presented. The controller includes a ramp generator for generating a ramp signal and a ramp adjuster. The ramp adjuster compares a feedback signal of the converter with a threshold signal to obtain a comparison signal, and to adjust an amplitude of the ramp signal based on the comparison signal. Also presented is a constant on time COT power converter including the above controller.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a signal cancellation circuit, a sampling circuit, a negative feedback circuit, an AD converter, and an addition-and-subtraction circuit.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.

Abstract: A semiconductor device includes: a constant current generating circuit unit; a first current mirror circuit unit having a constant current as an input current and generating a first mirror current as a mirror current; a level shift circuit unit including a clamp transistor between whose drain and source a first mirror current flows and to whose base a power supply voltage of the constant current generating circuit unit is applied, and a transistor that is connected in series to the clamp transistor and through which the first mirror current flows; a second current mirror circuit unit having as an input stage a transistor and having as an output stage a transistor through which a second mirror current replicating the first mirror current flows; and an error absorption circuit unit connected to a terminal for outputting the second mirror current of the output-stage transistor in the second current mirror circuit unit.

Abstract: A semiconductor device is provided. The semiconductor device includes an input/output cell, a core logic circuit, a first power supply cell, a second power supply cell, a third power supply cell and a fourth power supply cell. Each of the power supply cells includes a protection circuit and a bidirectional diode.

Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

Abstract: A semiconductor device capable of operating accurately while suppressing the propagation of interference noise, a control method for the semiconductor device, and a control program are provided. The semiconductor device includes a first AD converter of a charge redistribution type sequential comparison type that includes a redundant comparison operation in a sequential comparison operation and outputs a first input signal of an analog differential using a reference voltage to a first output signal of digital, a first pin to which the reference voltage is supplied from the outside, a first variable impedance circuit provided on a signal line between the first AD converter and capable of changing impedance, and a first control circuit 10 that controls the impedance of the first variable impedance circuit according to the operating condition of the first AD converter.

Abstract: A semiconductor device includes: a camera lens that controls an X axis, a Y axis, and a Z axis to perform camera shake correction; a first semiconductor chip that receives data of the X axis and the Y axis of the camera lens; a second semiconductor chip that receives data of the Z axis of the camera lens; and a gyro sensor that acquires camera shake state data, in which the second semiconductor chip is connected to the first semiconductor chip via a chip select signal line, a data signal line, and a clock signal line of SPI communication, and is connected to the gyro sensor via the chip select signal line, the data signal line, and the clock signal line of the SPI communication, and the second semiconductor chip transmits position data of the Z axis to a storage unit of the gyro sensor via the SPI communication.

Abstract: A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.

Abstract: A semiconductor device includes a first well region, a second well region, a body region, and a cathode region. The impurity concentration of the body region is higher than the impurity concentration of the first well region, and the impurity concentration of the second well region is higher than the impurity concentration of the body region. In plan view, the body region includes the cathode region, and the cathode region includes the second well region. The cathode region configures a cathode of a Zener diode, and the first well region, the second well region, and the body region configure an anode of the Zener diode.

Abstract: A switching converter is presented. The switching converter has a high side power switch coupled to a low side power switch at a switching node, a driver and a timing circuit. The driver generates a drive signal having a on-time to drive the high side power switch. The timing circuit generates a control signal to adjust the on-time during a load transient period.

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.