Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11915975
    Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 27, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Yoshida, Tomohiro Tomizawa
  • Patent number: 11915032
    Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 27, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Sugita
  • Patent number: 11909247
    Abstract: Semiconductor device includes a controller for controlling a charging of a battery cell. When the battery cell is charged, the controller generates a voltage command value which instructs to a charger so that an upper limit value of an output voltage output from the charger is higher than a predetermined voltage which is a maximum potential voltage that the battery cell can be charged maximally.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: February 20, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Uchinohae, Youhei Kengoyama
  • Patent number: 11907681
    Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 20, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa
  • Patent number: 11901288
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Uchida
  • Patent number: 11899564
    Abstract: A debug apparatus for performing allocation of target programs in which temperature is uniformized is provided. The debug apparatus receives temperature data measured by temperature sensors from a semiconductor device. The debug apparatus determines, as an analysis result of the temperature data, a CPU where the number of target programs executed is to be decreased and a CPU where the number of target programs executed is to be increased. The debug apparatus changes allocation of the target programs executed by a plurality of CPUs in the semiconductor device based on the analysis result of the temperature data.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoyoshi Ujii, Yuki Mori, Kazunori Ochiai
  • Patent number: 11901298
    Abstract: A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenji Ikura
  • Publication number: 20240044990
    Abstract: A semiconductor device, a battery pack, a method of controlling the semiconductor device, and a control program capable of accurately measuring a remaining capacity of a battery is provided. The semiconductor device includes: a current measurement circuit configured to measure a current value of a first current supplied from a battery to the semiconductor device that is a host device and a current value of a second current supplied from the battery to a load; and a computing circuit configured to calculate the remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 8, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Gen NAGASHIMA
  • Publication number: 20240039756
    Abstract: A CAN communication controller and a method of operating a CAN communication controller are disclosed. The CAN communication controller is for transmitting first and second types of frames wherein the first type of frame is used to transmit event-triggered communication data and the second type of frame is used to transmit best effort traffic data, the CAN communication controller configured, in response to transmitting a frame of the second type having a given identifier, to delay arbitration of a following frame of the second type having the given identifier, and not to delay arbitration of a frame of the first type.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 1, 2024
    Applicant: Renesas Electronics Corporation
    Inventors: Christian MARDMÖLLER, Tobias BELITZ
  • Publication number: 20240039492
    Abstract: A differential amplifier includes a first differential amplifier circuit as a first stage, a second differential amplifier circuit having a common mode feedback circuit in a second stage, and a feedback differential circuit configured to multiply a differential signal between a differential output of the first differential amplifier circuit and a differential input of the second differential amplifier circuit by a magnitude of a differential output of the common mode feedback circuit.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 1, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Nobuyuki MORIKOSHI
  • Patent number: 11887935
    Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: January 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 11886271
    Abstract: A semiconductor device which is a processor includes a plurality of first power supply regions in each of which a functional module having a predetermined function is arranged and to which a power supply voltage is individually supplied, a setting unit configured to specify an order of supplying the power supply voltage in the plurality of first power supply regions, and a power controller configured to supply the power supply voltage to the plurality of first power supply regions in accordance with the order specified by the setting unit.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayoshi Shiraishi, Tomohiro Katayama
  • Patent number: 11882697
    Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shu Shimizu
  • Patent number: 11880718
    Abstract: Example implementations includes a method of partitioning a non-transitory memory device by detecting a boot state of a processing device including a non-transitory memory device, identifying a startup state of the processing device based on the boot state, and partitioning the memory device into at least one secure address region, in accordance with a determination that the startup state satisfies an operating state condition. Example implementations also include a method of generating a secure partition associated with a non-transitory memory device by identifying a target processing instruction restricted to execution at a secure subsystem of a processing device, assigning to the target processing instruction a secure address, associating the secure address with a secure address region of a non-transitory memory device of the processing device, and generating a secure partition table including the secure address.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 23, 2024
    Assignee: Renesas Electronics Corporation
    Inventors: David Noverraz, Paul Bell, Kennedy Ho
  • Patent number: 11881806
    Abstract: A resolver converter includes a tracking loop circuit that calculates an angle ? from a resolver output signal, a control and diagnosis circuit that controls the tracking loop circuit and diagnoses based on the resolver output signal, wherein the control and diagnosis circuit, by operating the tracking loop circuit as a direct digital synthesizer (DDS), synchronously detects a noise signal superimposed on the resolver output signal.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Umamichi
  • Publication number: 20240022211
    Abstract: A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 18, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Soshiro NISHIOKA
  • Patent number: 11876879
    Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: January 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Dnyaneshwar Kulkarni, Thorsten Hoffleit
  • Patent number: 11876127
    Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu
  • Patent number: 11868277
    Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Sugita
  • Patent number: 11868654
    Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takanori Moriyasu, Kazuo Yoshihara, Takayuki Nishiyama