Abstract: A data processing device includes: an input data determining unit configured to determine whether or not each of binarized input data is a predetermined value; a storage unit configured to store a plurality of coefficients and coefficient address information including information related to coefficient addresses where the plurality of coefficients are stored; a control unit configured to read the coefficient address from the storage unit based on a determination result of the input data determining unit and read the coefficient from the storage unit based on the coefficient address; and an arithmetic unit configured to execute an arithmetic operation related to the coefficient acquired by the control unit.

Abstract: A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.

Abstract: A power converter controller is presented. The controller includes a ramp generator for generating a ramp signal and a ramp adjuster. The ramp adjuster compares a feedback signal of the converter with a threshold signal to obtain a comparison signal, and to adjust an amplitude of the ramp signal based on the comparison signal. Also presented is a constant on time COT power converter including the above controller.

Abstract: A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

Abstract: A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring. The first signal wiring is arranged in a region overlapping with a portion of a heat radiating plate. The second signal wiring is not arranged in the region. The ground plane has an opening portion located at a position overlapping with the first signal wiring. The opening portion is formed so as to extend along the first signal wiring.

Abstract: A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a signal cancellation circuit, a sampling circuit, a negative feedback circuit, an AD converter, and an addition-and-subtraction circuit.

Abstract: A semiconductor device includes: a constant current generating circuit unit; a first current mirror circuit unit having a constant current as an input current and generating a first mirror current as a mirror current; a level shift circuit unit including a clamp transistor between whose drain and source a first mirror current flows and to whose base a power supply voltage of the constant current generating circuit unit is applied, and a transistor that is connected in series to the clamp transistor and through which the first mirror current flows; a second current mirror circuit unit having as an input stage a transistor and having as an output stage a transistor through which a second mirror current replicating the first mirror current flows; and an error absorption circuit unit connected to a terminal for outputting the second mirror current of the output-stage transistor in the second current mirror circuit unit.

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

Abstract: An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. The silicon film and the insulating film in a transistor forming region are removed, and the silicon film and the insulating film in a transistor forming region are left. An insulating film is formed on the semiconductor substrate in the transistor forming region. A Hf-containing film is formed on the insulating film and the silicon film, and a silicon film is formed on the Hf-containing film. Then, a gate electrode is formed by patterning the silicon film, and a gate electrode is formed by patterning the silicon film. A gate insulating film under the gate electrode is formed by the insulating film, and a gate insulating film under the gate electrode is formed by the insulating film and the Hf-containing film.

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

Abstract: A semiconductor device is provided. The semiconductor device includes an input/output cell, a core logic circuit, a first power supply cell, a second power supply cell, a third power supply cell and a fourth power supply cell. Each of the power supply cells includes a protection circuit and a bidirectional diode.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.

Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

Abstract: A technique capable of normally transmitting a LPM token from a transceiver to a USB device is provided. A semiconductor device includes: a controller including a first interface circuit in conformity with UTMI+ standards; a converting circuit including a second interface circuit in conformity with the UTMI+ standards and a third interface circuit in conformity with ULPI standards, the second interface circuit converting data transmitted from the first interface circuit and received, and the third interface circuit transmitting the converted data; a first circuit analyzing a packet output from the controller and identifying and holding a packet identifier contained in the packet; and a second circuit providing a transmission command, after which a data string containing the packet identifier indicating LPM bringing a USB device to a low power consumption state is added, if the first circuit determines that the packet identifier is the LPM.