Abstract: A torque map generation system includes a motor, an inverter that drives the motor, a controller that controls the inverter, a torque sensor coupled to the motor, a power analyzer coupled to the torque sensor and a torque map generator that measures a current vector value of the motor by switching a MTPA (Maximum Torque Per Ampere) method and a square wave method based on a voltage utilization ratio of the inverter, wherein the torque map generator utilizes a measurement result by the MTPA method when the torque map generator uses the square wave method.

Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

Abstract: Apparatuses, systems and methods for operating a power amplifier are described. A controller can drive a power amplifier chain with first input bias voltages to operate the power amplifier chain in a first operation mode that implements a Doherty amplifier. The controller can drive the power amplifier chain with second input bias voltages to operate the power amplifier chain in a second operation mode that implements a balanced amplifier. The controller can tune the termination circuit in accordance with an operation mode of the power amplifier chain.

Abstract: An apparatus comprising a bias current generator for generating a bias current, the bias current generator comprising two or more negative threshold transistors of the same type and coupled in series.

Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.

Abstract: A filter circuit for use with a system configured to be coupled with an electrical load, the filter circuit comprising a first filter, wherein the first filter is configured to receive a first voltage and provide an output voltage, the output voltage being the first voltage after filtering by the first filter, and the filter circuit is configured to adjust the bandwidth of the first filter in response to a load transient.

Abstract: A self-starting bandgap cell for generating a reference voltage.

Abstract: A low dropout regulator for providing an output voltage, the low dropout regulator comprising a resistive device configured to contribute to the stability of the low dropout regulator during operation and to have a resistance that is dependent on a load current.

Abstract: It is an object of the present invention to provide a technique capable of easily extracting a section signal of a specific sub-process. The anomaly detection system includes an extraction unit for extracting a specific subsequence to be an object of anomaly detection from among a plurality of subsequences from a composite sequence included in a monitor signal. The extraction unit determines an optimal warping path from the composite sequence and a reference sequence, which is an example of the composite sequence acquired in advance, by a dynamic time warping method. The extraction unit identifies a start point and an end point of a specific subsequence based on the optimal warping path and the start point and end point of the subsequence of the reference sequence. The extraction unit extracts a specific subsequence based on a start point and an end point of the specific subsequence.

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

Abstract: A semiconductor device includes a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate. The ferroelectric film and a metal film are not formed just above an element isolation region formed in a trench in an upper surface of the semiconductor substrate, but are formed on the semiconductor substrate in the active region defined by the element isolation region to prevent a state in which a polarization state in the ferroelectric film of the active region and a polarization state in the ferroelectric film on the element isolation region differ from each other.

Abstract: A first semiconductor element (laser diode) and a second semiconductor element (laser diode) are connected to each other in series between a wiring electrically connected to an anode of the first semiconductor element and a wiring electrically connected to a cathode of the second semiconductor element. In this case, each of the first semiconductor element and the second semiconductor element includes a laminated pattern having an emission layer and a plurality of semiconductor layers covering this laminated pattern.

Abstract: The semiconductor device includes a frequency output circuit that outputs a clock signal having a specified frequency, a circuit block that realizes a predetermined function, and a standby controller that controls a standby mode of the circuit block in accordance with the clock signal. Here, the standby controller includes a control circuit that outputs state information corresponding to the control of the standby mode, a frequency control signal that designates the frequency of the clock signal output from the frequency output circuit in accordance with the state information, and a frequency selection circuit that outputs count information that designates the duration of the state transition of the circuit block.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: A programmable gain amplifier provided in a semiconductor device includes a fully differential amplifier configured to amplify differential input voltages having an offset voltage. First and second correction voltages are input to a non-inverting input node and an inverting input node of the fully differential amplifier via first and second resistance elements, respectively.

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.