Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11128131
    Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohiro Yoshimura, Osamu Soma
  • Patent number: 11126435
    Abstract: A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masanao Sasai
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11126373
    Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsunori Hirobe
  • Patent number: 11120862
    Abstract: A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: September 14, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichi Takeda
  • Patent number: 11119948
    Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 14, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Ichikawa
  • Patent number: 11112624
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Tohru Kawai
  • Patent number: 11115235
    Abstract: A semiconductor device capable of improving the efficiencies of communication systems is provided. The semiconductor device comprises: an open period in which reception of data or transmission is allowed; a clock generation circuit defining a close period in which transmission of data and reception are not allowed; and a TSN controller connected to the clock generation circuit and performing transmission of data or reception, wherein the TSN controller performs semiconductor device or reception at another time than open period.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichiro Sano, Jean Noel Mouthe
  • Patent number: 11115614
    Abstract: The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichi Iizuka, Fukashi Morishita
  • Patent number: 11113218
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki
  • Patent number: 11114962
    Abstract: The present disclosure starts up a three-phase motor in a stable manner. During a start-up operation of a brushless DC motor, a motor drive system detects the position of a particularly suitable rotor while the rotor is resting, and applies a drive current to two phases in accordance with the detected position of the rotor. A controller changes the time of drive current application in accordance with the magnitude of back electromotive force that is in a non-conducting phase and detected by a detector during drive current application.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Patent number: 11114527
    Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 7, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Koshimizu, Hideki Niwayama, Kazuyuki Umezu, Hiroki Soeda, Atsushi Tachigami, Takeshi Iijima
  • Patent number: 11107539
    Abstract: The semiconductor device includes a semiconductor chip including a first nonvolatile memory including a first memory block and a second memory block, CPU controlling the first nonvolatile memory, a first switch electrically connected to the first memory block and controlling the supply of the first power supply voltage to the first memory block, a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block, and a second nonvolatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, wherein the control of each of the first switch and the second switch is performed based on flag information indicating whether program data executed by CPU is written in the first memory block and the second memory block.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 31, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kotaro Sakumura, Hiroshi Tachibana, Hideki Otsu
  • Patent number: 11107912
    Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 31, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 11101206
    Abstract: The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Okayasu, Shuuichi Kariyazaki
  • Patent number: 11101281
    Abstract: The semiconductor device includes a fin FA selectively protruded from an upper surface of a semiconductor substrate SB, a gate insulating film GF1 formed on an upper surface and a side surface of the fin FA and having an insulating film X1 and a charge storage layer CSL, and a memory gate electrode MG formed on the gate insulating film GF1. Here, the thickness of the charge storage layer CSL on the upper surface of the fin FA is larger than the thickness of the charge storage layer CSL on the side surface of the fin FA.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shibun Tsuda
  • Patent number: 11100019
    Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Hiraki, Sho Yamanaka
  • Patent number: 11102475
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Maiki Hosokawa, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki, Tomohiro Une, Kazushi Akie
  • Publication number: 20210258136
    Abstract: An integrated circuit, for example, a system-on-a-chip is disclosed. The integrated circuit includes a timing synchronisation unit including a hardware timer, for example, a gPTP timer. The integrated circuit also includes a non-Ethernet network interface, for example, a PCIe interface, for communicating with another integrated circuit having another hardware timer. The timing synchronisation unit is configured, in response to receiving a timing trigger from the other integrated circuit, to capture a local time t2. The timing synchronisation unit is further configured to provide the local time t2 to a processor for the processor to compute a timing offset between a remote time t1 of the other hardware timer which generated the timing trigger and the local time for time synchronisation.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 19, 2021
    Applicant: Renesas Electronics Corporation
    Inventors: Thorsten HOFFLEIT, Christian MARDMOELLER, Hansjoerg BERBERICH
  • Patent number: 11094037
    Abstract: A semiconductor device includes an image data acquisition circuit which acquires a plurality of first captured image data and a plurality of second captured image data at a first time and a second time, an adjustment region determination circuit which detects a target object from the plurality of first captured image data, and determines an adjustment region by estimating a position of the target object at the second time, a color adjustment circuit configured to determine a color adjustment gain based on the adjustment region, and perform color balance adjustment processing on the plurality of second captured image data based on the color adjustment gain, and an image synthesis circuit configured to synthesize the plurality of second captured image data so that overlapping regions included in a plurality of images of the plurality of second captured image data overlap each other.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 17, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Kawaguchi, Akihide Takahashi