Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10419663
    Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Toshiyuki Kaya, Seiji Mochizuki, Ryoji Hashimoto
  • Patent number: 10419753
    Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazushi Akie, Seiji Mochizuki, Toshiyuki Kaya, Katsushige Matsubara, Hiroshi Ueda, Ren Imaoka, Ryoji Hashimoto
  • Patent number: 10419009
    Abstract: The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenichi Shibata
  • Patent number: 10418327
    Abstract: An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Toshifumi Suganaga
  • Patent number: 10416481
    Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 10418328
    Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kawamura
  • Patent number: 10418323
    Abstract: An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihisa Matsubara, Takashi Ishigami
  • Patent number: 10418321
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10418325
    Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Nishida, Naozumi Morino, Toshimi Mizutani
  • Patent number: 10416382
    Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Patent number: 10417973
    Abstract: An image processing device includes a luminance modulator operable to receive a video input signal and operable to calculate a video output signal to be supplied to a display panel, a peak value detector operable to calculate a peak value as a maximum luminance in a prescribed region of the video input signal, a histogram detector operable to calculate frequency distribution about a luminance value of the video input signal in the prescribed region, a peak Automatic contrast level (ACL) control gain calculation unit operable to calculate a peak ACL control gain with which luminance of each pixel of the video input signal is amplified, based on the ratio of the peak value to a maximum possible value of the video output signal, and a pattern-adaptive gamma characteristic calculation unit operable to calculate a luminance modulation gain.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hirofumi Kawaguchi
  • Patent number: 10418292
    Abstract: A subject matter of this invention is that a manufacturing yield of a semiconductor device is improved. A resistance value between a pogo pin and a test pin is measured by bringing a plurality of pogo pins of a socket mounted over a test board included in an inspection device of a semiconductor device into contact with a plurality of solder balls, respectively, and bringing the test pin provided in the socket into contact with a first solder ball of a plurality of solder balls at a position different from a position where the pogo pin is brought into contact with the first solder ball. Thereby, a coupling failure between the pogo pin and the first solder ball is detected, so that a conductive state is inspected.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yu Muto
  • Patent number: 10409260
    Abstract: To provide an abnormality detection system capable of reducing work load of an engineer. An algorithm storage unit stores therein a detection algorithm corresponding to identification information of a detection target. An abnormality detection unit detects an abnormality in a detection target signal obtained from a monitor signal of the detection target using a corresponding detection algorithm in the algorithm storage unit. A detection target identification unit determines whether the detection algorithm corresponding to the identification information of the detection target is stored in the algorithm storage unit, and issues a generation request when it is not stored therein. An algorithm generation unit generates the detection algorithm using a corresponding detection target signal according to the generation request.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masatoshi Kawatake
  • Patent number: 10409749
    Abstract: An SCI can perform transmission only or reception only, however, it is necessary to reset the SCI when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock. The interface circuit includes a register to specify an operation enabled state which is at least one of a transmit state and a receive state, and a mode control circuit to change at least one mode of transmit or receive in the operation enabled state.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Mitsuishi, Seiji Ikari
  • Patent number: 10410946
    Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohito Suzumura, Hideki Aono
  • Patent number: 10408687
    Abstract: According to one embodiment, a semiconductor device 1 includes a temperature sensor module 10 that outputs a non-linear digital value with respect to temperature and a substantially linear sensor voltage value with respect to the temperature, a storage unit 30 that stores the temperature, the digital value, and the sensor voltage value, and a controller 40 that calculates a characteristic formula using the temperature, the digital value, and the sensor voltage value stored in the storage unit 30, in which the temperature, the digital value, and the sensor voltage value stored in the storage unit 30 include absolute temperature under measurement of absolute temperature, the digital value at the absolute temperature, and the sensor voltage value at the absolute temperature.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanori Ikeda, Tadashi Kameyama
  • Patent number: 10411036
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 10411112
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki Tsunomura, Toshiaki Iwamatsu
  • Patent number: 10411025
    Abstract: In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n+-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n+-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihisa Matsubara
  • Patent number: 10411095
    Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiko Yoshioka