Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11456665
    Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Hashimoto, Kazuya Uejima
  • Patent number: 11456975
    Abstract: A communications network controller module for storing media data in memory is disclosed. The module comprises a media access controller and a message handler. The message handler is configured, in response to receiving a frame comprising frame data from the media access controller, to identify a frame type for the frame, to identify a target queue in dependence upon the frame type, the target queue comprising a series of data areas in memory reserved for storing frames of the frame type, to obtain a current descriptor address of a current descriptor for the target queue, the current descriptor comprising a descriptor type field, a descriptor pointer field and a descriptor data size field, and to obtain an address in the series of data areas, to store a part of the frame data at the data area address.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Dnyaneshwar Kulkarni, Christian Mardmöller
  • Patent number: 11456264
    Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiaki Sato, Mitsunobu Wansawa, Akira Matsumoto, Yoshinori Deguchi, Kentaro Saito
  • Patent number: 11456265
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 27, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Tonegawa
  • Patent number: 11455248
    Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nakamura, Akihiro Yamamoto, Kazuaki Terashima, Manabu Koike
  • Patent number: 11456692
    Abstract: A semiconductor device for controlling a three-phase motor with double windings, includes a first inverter that drives a first winding of the three-phase motor, a second inverter that drives a second winding of the three-phase motor and a communication line between the first and second inverters. The first and second inverters, through the communication line, notify a respective operation state each other.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naohiko Aoki
  • Patent number: 11455061
    Abstract: An object of the present invention is to provide an information input device capable of realizing high-precision touch operations. The information input device includes a first surface for displaying input request information, a second surface for inputting input request information, a viewpoint calculator for calculating a viewpoint direction of an input person, and a coordinate corrector for correcting a position input to the second surface into a second position in response to the viewpoint direction of the input person and inputs the input request information on the first surface corresponding to the second position. The information input device further provides a storage device for holding distance information on distance between the first surface and the second surface.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kentarou Niikura
  • Patent number: 11449361
    Abstract: In a semiconductor device according to the related art, unfortunately, a non-safety unit mounted on the same device as a safety unit is modified with low flexibility. According to one embodiment, a first semiconductor chip and a second semiconductor chip each have space domain separation hardware for limiting access to hardware resources in a functional safety system. Safety unit software and space domain and time domain separation software are executed in a time sharing manner. Based on a timer installed on the semiconductor chip, the space domain and time domain separation software performs separation for intermittently executing the safety unit software in a predetermined cycle, self-diagnosis for examining an operation of the safety unit software, and mutual diagnosis made between the first semiconductor chip and the second semiconductor chip to mutually diagnose the operation of the space domain and time domain separation software for performing the separation and the self-diagnosis.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 20, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiki Yamahira, Toshihiro Kawano
  • Patent number: 11450731
    Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: September 20, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiemi Hashimoto, Kosuke Yayama, Hidekazu Tawara
  • Patent number: 11450561
    Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: September 20, 2022
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
  • Patent number: 11440466
    Abstract: A semiconductor device has a position estimation part calculating an estimated position of a mobile at a scheduled time to project a message image, based on movement information of the mobile, a reference image signal output part deciding a reference area being an area to project a reference image, based on a relative positional relation between the mobile at the estimated position and the projection area, and outputting a reference image signal being a signal of the reference image, a test image signal acquisition part acquiring a test image signal being a signal of an image obtained by imaging the reference area with the reference image projected thereon, and an image adjustment part adjusting the message image signal, based on the reference image signal and the test image signal.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Kawaguchi, Koji Yasuda, Akihide Takahashi
  • Patent number: 11444557
    Abstract: A gate drive semiconductor device includes: external terminals to which PWM control signals are supplied; external terminals outputting a drive signal for driving a three-phase BLDC motor; external terminals to which the counter electromotive voltage generated by driving the three-phase BLDC motor is supplied; a zero-cross determination unit generating an interrupt signal indicating timing at which the counter electromotive voltage intersects with a midpoint potential of the three-phase BLDC motor based on the PWM control signal and the counter electromotive voltage; and an external terminal outputting the interrupt signal.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigi Ishiji, Minoru Kurosawa
  • Patent number: 11444186
    Abstract: A semiconductor device includes a semiconductor substrate, first and second trench electrodes formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first and second trench electrodes, a floating separation layer of a second conductivity type formed between the first and second trench electrodes and contacted with the floating layer of the first conductivity type and a floating layer control gate disposed on the floating separation layer of the second conductivity type.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 11444010
    Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazunori Hasegawa, Yuichi Yato, Hiroyuki Nakamura, Yukihiro Sato, Hiroya Shimoyama
  • Patent number: 11442426
    Abstract: According to semiconductor device includes a domain converter for converting a digitized resolver signal from a time-domain to a frequency-domain, a spectrum analyzer for analyzing a spectrum of the resolver signal converted to a frequency-domain by the domain converter, and an error detector for detecting an error related to the resolver signal based on an output signal from the spectrum analyzer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yutaka Oshima, Hisaaki Watanabe
  • Patent number: 11435645
    Abstract: A semiconductor device has a first semiconducting layer including an optical waveguide, a dielectric layer formed on the optical waveguide, and a conductive layer formed on the dielectric layer. A refractive index of a material of the conductive layer is smaller than a refractive index of a material of the first semiconductor layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: September 6, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 11435525
    Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 6, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 11437341
    Abstract: A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 6, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 11431378
    Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 30, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Ryuichi Oikawa
  • Patent number: 11422960
    Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 23, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kyohei Yamaguchi, Daisuke Kawakami, Hiroyuki Hamasaki