Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11158597
    Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Shiroi, Shuuichi Kariyazaki
  • Patent number: 11153131
    Abstract: Increase the effective data rate of high-speed data communication. It has a memory unit, a reception signal line, and a transmission signal line capable of communicating with an external device via a control circuit and an equalizer, controllers for controlling transmission and reception of signals to and from the external device, and a correction coefficient associated with an identification information and the identification information of the external device. The control circuit sets the correction coefficient associated with the identification information to the equalizer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kouji Ueta
  • Patent number: 11152393
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 19, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 11152353
    Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fujio Shimizu, Tsuyoshi Kachi, Yoshinori Yoshida
  • Patent number: 11145597
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Teruhiro Kuwajima
  • Patent number: 11145744
    Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichiro Abe, Takashi Hashimoto, Hideaki Yamakoshi, Yuto Omizu
  • Patent number: 11146074
    Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yu Kinoshita
  • Patent number: 11145093
    Abstract: A semiconductor device includes an image acquisition circuit which acquires a plurality of captured image data obtained by capturing a plurality of images, an estimation source image generation circuit which cancels effects of initial color adjustment processing on each captured image data to generate image data of a plurality of estimation source images, a readjustment circuit which divides each estimation source image into a plurality of processing regions to perform color balance readjustment processing for each processing region, and an image synthesis circuit which synthesizes the image data of the plurality of estimation source images so that overlapping regions included in the estimation source images overlap each other to generate image data of a synthesized image.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Kawaguchi, Akihide Takahashi
  • Patent number: 11146309
    Abstract: The power line communication device detects inverter noise from the voltage waveforms of the power line, and executes the output of the transmission signal in a period in which it is determined that the signal amplitude of the transmission signal in the transmission processing unit exceeds a predetermined value from the output amplitude of the inverter noise, and stops the output of the transmission signal in other periods.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kosuke Shibuya, Yoshitaka Shibuya
  • Patent number: 11137560
    Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 11139240
    Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 11139749
    Abstract: A semiconductor device includes a rectifier circuit that rectifies an AC input voltage, a zero-cross detection circuit that detects a zero-cross of the AC input voltage, a control circuit that turns on the rectifier circuit at a timing determined by the zero-cross detected by the zero-cross detection circuit and a predetermined phase angle, and the phase angle is set so that an output voltage of the rectifier circuit is gradually increased.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshihiro Miyazaki
  • Patent number: 11137937
    Abstract: A master issues the valid data is specified when the data update processing is interrupted. The control unit 3 stores in the storage unit 2 the second update status flag 8_2, which indicates the update status of the first update status flag 8_1 and the second data 6_2, which indicate the update status of the first data 6_1, and the third update status flag 8_3, which indicates the update status of the valid indication flag 7. When the determination based on the valid instruction flag 7 is impossible, the usage data determination unit 4 determines which of the first data 6_1 and the second data 6_2 is valid based on the values of the first update status flag 8_1, the second update status flag 8_2, and the third update status flag 8_3.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Kurafuji, Satoshi Yamamoto
  • Patent number: 11133326
    Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Takizawa, Tomoya Saito
  • Patent number: 11133422
    Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masao Inoue
  • Patent number: 11133753
    Abstract: A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Kaeriyama
  • Patent number: 11133393
    Abstract: The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobue Maekawa
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11126435
    Abstract: A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masanao Sasai
  • Patent number: 11128131
    Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohiro Yoshimura, Osamu Soma