Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10790277
    Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Maeda, Yasuyuki Morishita, Masanori Tanaka
  • Patent number: 10790355
    Abstract: In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 29, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Shinkawata
  • Patent number: 10790683
    Abstract: A semiconductor device includes a control unit which controls charging/discharging of a secondary battery, a bidirectional coupling unit which is electrically coupled to the control unit and through which a charging/discharging current flows, and a protection diode coupled between the control unit and the bidirectional coupling unit. The bidirectional coupling unit includes a discharging power transistor, a charging power transistor reversely coupled in series with the discharging power transistor, and a common drain pad which functions as a drain of the discharging power transistor and further functions as a drain of the charging power transistor. An anode of the protection diode is electrically coupled to the common drain pad. A cathode of the protection diode is electrically coupled to a power supply terminal of the control unit.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Mochizuki, Kensuke Nakashima, Takahiro Korenari, Kouji Nakajima
  • Patent number: 10782886
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nhat Van Huynh, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Patent number: 10784801
    Abstract: The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Minoru Kurosawa, Kichiya Itagaki
  • Patent number: 10784905
    Abstract: To provide a communication device that can suppress radio wave interference in communication using a plurality of frequency signals in a simply method, a communication device includes a first communication unit that communicates with a first external device by using a first frequency signal, a second communication unit that communicates with a second external device by using a second frequency signal, and a control unit that controls, when one of the first and second communication units transmits data to a corresponding one of the first and second external devices, the other of the first and second communication units not to receive data.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Sagesaka, Suguru Fujita
  • Patent number: 10782763
    Abstract: A semiconductor device includes a voltage sensor which samples a power supply voltage at a speed faster than fluctuations in the power supply voltage and encodes the power supply voltage into a voltage code value. A voltage drop determination circuit detects a voltage drop based on the voltage code value, and a clock control circuit generates a clock. The clock control circuit stops the clock when the voltage drop determination circuit detects the voltage drop. The voltage drop determination circuit includes a prediction computation circuit which looks ahead a voltage value from a history of the voltage code value and predicts a variation value, and the prediction computation circuit includes a circuit for masking a prediction value if a differential value of the prediction value is continuously negative for a predetermined cycle.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuko Kitaji, Kazuki Fukuoka, Ryo Mori, Toshifumi Uemura
  • Patent number: 10777293
    Abstract: To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomonori Sasaki, Tatsuya Saito, Hideshi Maeno, Takeshi Ueki
  • Patent number: 10777475
    Abstract: In order to improve reliability of a semiconductor device, in a semiconductor chip according to one embodiment, an uneven shape is formed on an exposed surface of a back surface electrode formed on a back surface of the semiconductor chip.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiro Fukuchi
  • Patent number: 10777569
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuto Omizu, Takashi Hashimoto, Hideaki Yamakoshi
  • Patent number: 10777507
    Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Patent number: 10777490
    Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Toshinori Kiyohara
  • Patent number: 10777688
    Abstract: In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved. An insulating film is formed between an upper surface of a fin and each of a control gate electrode and a memory gate electrode in a memory cell region, so that in a gate insulating film of each of a control transistor and a memory transistor, thickness of a portion on the fin is larger than thickness of a portion covering side surfaces of the fin. The insulating film having a bird's beak at its end portion is formed to round a corner of the fin.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Hayashi
  • Patent number: 10766405
    Abstract: To provide a semiconductor device which suppresses a message image projected by a mobile from varying from a desired position. A semiconductor device has a first area decision part which decides a first area onto which a message image is projected, based on movement information of a mobile. The semiconductor device has a delay period calculation part which calculates a delay period being a period from a first time for projecting the message image onto the first area to a second time when the message image is projectable. Also, the semiconductor device has a second area decision part which adjusts the first area, based on the delay period to decide a second area. Further, the semiconductor device has an image signal conversion part which converts a message image signal according to the second area.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Yasuda, Hirofumi Kawaguchi, Akihide Takahashi
  • Patent number: 10770160
    Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 8, 2020
    Assignees: Attopsemi Technology Co., LTD, Renesas Electronics Corporation
    Inventors: Shine C. Chung, Koji Nii
  • Patent number: 10770375
    Abstract: A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip. The die pad includes a wire-bonding region to which the wire is connected and a through hole penetrating through the die pad in a thickness direction. The wire-bonding region is covered by a metal film partially covering the die pad. The through hole is formed at a position overlapping the metal film. The encapsulation body includes a first portion formed over the die pad, a second portion formed under the die pad, and a third portion buried in the through hole of the die pad, wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: September 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Jun Shibata
  • Publication number: 20200280291
    Abstract: Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (211), each path respectively comprising, an input terminal (221), an output terminal (231), a node (241) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND).
    Type: Application
    Filed: July 31, 2017
    Publication date: September 3, 2020
    Applicant: Renesas Electronics Corporation
    Inventor: Mohsen Naghed
  • Patent number: 10763336
    Abstract: A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi Yanagigawa
  • Patent number: 10763214
    Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Kazuyuki Nakagawa, Keita Tsuchiya, Yosuke Katsura, Shinji Katayama, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
  • Patent number: 10764387
    Abstract: There is a need to acquire more reliable profile information without relying on only the personal subjective judgment on the profile information. Profile information about a dweller is automatically extracted by evaluating and comprehensively determining each of feature amounts concerning the dweller from sensing data acquired from a sensor or a usage log concerning an equipment instrument in a living space based on a criterion for the feature amounts predetermined for a profile item. The reliability of the self-reported profile information is evaluated by comparing and verifying the automatically extracted profile information with the self-reported profile information supplied by the dweller.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Kurihara, Takehiro Mikami