Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10777293
    Abstract: To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomonori Sasaki, Tatsuya Saito, Hideshi Maeno, Takeshi Ueki
  • Patent number: 10777569
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuto Omizu, Takashi Hashimoto, Hideaki Yamakoshi
  • Patent number: 10777490
    Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Toshinori Kiyohara
  • Patent number: 10777688
    Abstract: In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved. An insulating film is formed between an upper surface of a fin and each of a control gate electrode and a memory gate electrode in a memory cell region, so that in a gate insulating film of each of a control transistor and a memory transistor, thickness of a portion on the fin is larger than thickness of a portion covering side surfaces of the fin. The insulating film having a bird's beak at its end portion is formed to round a corner of the fin.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Hayashi
  • Patent number: 10777507
    Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Patent number: 10770160
    Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 8, 2020
    Assignees: Attopsemi Technology Co., LTD, Renesas Electronics Corporation
    Inventors: Shine C. Chung, Koji Nii
  • Patent number: 10766405
    Abstract: To provide a semiconductor device which suppresses a message image projected by a mobile from varying from a desired position. A semiconductor device has a first area decision part which decides a first area onto which a message image is projected, based on movement information of a mobile. The semiconductor device has a delay period calculation part which calculates a delay period being a period from a first time for projecting the message image onto the first area to a second time when the message image is projectable. Also, the semiconductor device has a second area decision part which adjusts the first area, based on the delay period to decide a second area. Further, the semiconductor device has an image signal conversion part which converts a message image signal according to the second area.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Yasuda, Hirofumi Kawaguchi, Akihide Takahashi
  • Patent number: 10770375
    Abstract: A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip. The die pad includes a wire-bonding region to which the wire is connected and a through hole penetrating through the die pad in a thickness direction. The wire-bonding region is covered by a metal film partially covering the die pad. The through hole is formed at a position overlapping the metal film. The encapsulation body includes a first portion formed over the die pad, a second portion formed under the die pad, and a third portion buried in the through hole of the die pad, wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: September 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Jun Shibata
  • Publication number: 20200280291
    Abstract: Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (211), each path respectively comprising, an input terminal (221), an output terminal (231), a node (241) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND).
    Type: Application
    Filed: July 31, 2017
    Publication date: September 3, 2020
    Applicant: Renesas Electronics Corporation
    Inventor: Mohsen Naghed
  • Patent number: 10763336
    Abstract: A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi Yanagigawa
  • Patent number: 10761139
    Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
  • Patent number: 10763214
    Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Kazuyuki Nakagawa, Keita Tsuchiya, Yosuke Katsura, Shinji Katayama, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
  • Patent number: 10764387
    Abstract: There is a need to acquire more reliable profile information without relying on only the personal subjective judgment on the profile information. Profile information about a dweller is automatically extracted by evaluating and comprehensively determining each of feature amounts concerning the dweller from sensing data acquired from a sensor or a usage log concerning an equipment instrument in a living space based on a criterion for the feature amounts predetermined for a profile item. The reliability of the self-reported profile information is evaluated by comparing and verifying the automatically extracted profile information with the self-reported profile information supplied by the dweller.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: September 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Kurihara, Takehiro Mikami
  • Patent number: 10756115
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Patent number: 10748933
    Abstract: Provided is a semiconductor device in which influence resulting from a cell function change can be reduced. The semiconductor device includes a function cell designed using a basic cell including a first wiring layer provided over a main surface of a semiconductor substrate and having a predetermined pattern and a second wiring layer provided over the first wiring layer and having a predetermined pattern. The function cell corresponds to the basic cell which is modified to have a predetermined function by changing the pattern of the second wiring layer at a design stage. The function cell has a first layout and a second layout which are disposed in juxtaposition in one direction in a plane parallel with the main surface. The function cell is provided with the predetermined function by coupling together wires belonging to the respective second wiring layers of the first layout and the second layout.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Yadoguchi, Takashi Fujii
  • Patent number: 10749026
    Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Yoshida, Tsuyoshi Kachi
  • Patent number: 10749363
    Abstract: Provided are a semiconductor device, a battery system, and a battery control method that are capable of reducing difference in remaining capacity without regard to the load status of a battery pack. The semiconductor device includes a high-voltage resistant circuit and a low-voltage circuit. The high-voltage resistant circuit includes a multiplexer that selects one of multiple series-coupled battery cells in a battery pack and couples the selected battery cell to the battery pack. The low-voltage circuit includes a measurement circuit that individually measures voltages of the battery cells. The multiplexer couples one of the battery cells to a power supply for the low-voltage circuit.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshiya Kamibayashi
  • Patent number: 10750090
    Abstract: A semiconductor device for use in controlling a camera module performs position adjustment of a correction lens for use in optical camera shake correction, based on information representing a present position of the correction lens and position information of an output image of electronic camera shake correction with respect to a photographed image photographed by an imaging element. As a result, an operation margin of the correction lens is kept, while keeping a correction margin for the electronic camera shake correction.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Murashima
  • Patent number: 10749510
    Abstract: A semiconductor device includes a first oscillator circuit, a clock monitoring circuit and a timing signal generation circuit for periodically switching the operating mode of the clock monitoring circuit to one of the first to third modes. The clock monitoring circuit includes: a clock counter configured for counting the number of oscillations of the clock signal in the first mode and configured for shifting the pulses of the input signal to the output signal at normal time in the third mode; a comparison circuit for comparing whether the count value per predetermined period by the clock counter is within an expected value in the second mode; and an edge detection circuit for detecting whether the pulses of the input signal are shifted to the output signal of the clock counter in the third mode.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasunori Kubota
  • Patent number: 10749517
    Abstract: A semiconductor device includes a first main MOS transistor and a second main MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode and a first sense MOS transistor and a second sense MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode. The first sense MOS transistor is used for detecting the main current of the first main MOS transistor, and the second sense MOS transistor is used for detecting the main current of the second main MOS transistor.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kouji Nakajima, Yoshiaki Tanaka