Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11088111
    Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 10, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Takayanagi
  • Patent number: 11081596
    Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Kadoshima, Masao Inoue
  • Patent number: 11079539
    Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 11081994
    Abstract: A semiconductor device for vector control of an AC motor via an inverter, includes a dq-axis reference current value generator which generates dq-axis reference current values, a three-phase/two-phase converter which generates dq-axis detected current values from three-phase current values of the inverter and a rotor position of the AC motor, a current controller generates dq-axis reference voltage values by proportional control and proportional integral control based on the dq-axis reference current values, the dq-axis detected current values, a rotation angular speed of the AC motor, and a motor parameter setting value, wherein the integration controller provides an initial voltage value to an integrator before switching to the proportional integral control, and wherein the initial voltage value is based on the dq-axis reference current values, the dq-axis detected current values, the rotation angular speed, the motor parameter setting value, and one of a proportional gain and the dq-axis reference voltage
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hengquan Jin, Guanyuan Chen, Chengzhe Li
  • Patent number: 11081454
    Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Patent number: 11079972
    Abstract: The memory includes a first descriptor area and a first data area corresponding to the first OS, and a second descriptor area and a second data area corresponding to the second OS. The second processor stores the first transmission instruction information corresponding to the transmission data stored in the second data area in the second descriptor area and transmits a first update notification of the second descriptor area to the first processor. In response to the first update notification, the first processor reads the first transmission instruction information stored in the second descriptor area and stores the first transmission instruction information in the first descriptor area. The communication circuit controlled by the first processor performs transmission process of transmission data stored in the second data area based on the first transmission instruction information stored in the first descriptor area.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaru Nagai
  • Patent number: 11079540
    Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 11081581
    Abstract: The n-type body extension region BER is separated from the n+ buried region BL by the p-type impurity region PIR and is in contact with the p-type drift region DFT1. At the end of the n-type body extension region BER closest to the p+ drain region DC, the first portion FP of the n-type body extension region BER located closest to the second surface SS is located closer to the p+ drain region DC than the second portion SP of the n-type body extension region BER located at the first surface FS, and is located closer to the second surface SS than the bottom surface BS of the element isolation insulating film SIS.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuji Ishii
  • Patent number: 11081169
    Abstract: A semiconductor device has a first memory circuit comprising a first memory cell comprising a first field effect transistor, a second memory circuit comprising a second memory cell comprising a second field effect transistor, and a regulator for converting the first power supply potential to a second voltage value lower than the voltage value of the first power supply potential. The second gate length of the second field effect transistor is longer than the first gate length of the first field effect transistor, the first memory cell is supplied with a second power supply potential through regulator, and the second memory cell is supplied with a first power supply potential.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Nakamura, Yoshisato Yokoyama
  • Patent number: 11081491
    Abstract: There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiraku Chakihara
  • Patent number: 11081438
    Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiaki Sato, Yoshinori Miyaki, Junichi Arita
  • Patent number: 11076123
    Abstract: A photographing control device capable of storing images to be stored at appropriate timings is provided. The analysis result acquiring unit acquires an analysis result of an image obtained by photographing an object by the photographing device. The status acquisition unit acquires a detection result obtained by detecting the status of the object by the sensor. The index determination unit determines the degree of these indexes for each of a plurality of indexes including those relating to the object based on the image analysis result and the detection result of the state of the object. The evaluation value calculation unit calculates an evaluation value for evaluating the stored value of the image using the degree of the index. When the evaluation value exceeds a predetermined threshold value, the image storage control unit 15 controls so as to store an image.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehito Baba
  • Patent number: 11069581
    Abstract: The reliability of the semiconductor device is suppressed from deteriorating. A first gate electrode is formed on the semiconductor layer SM located in the SOI region 1A of the substrate 1 having the semiconductor base material SB, the insulating layer BX, and the semiconductor layer SM via the first gate insulating film, a second gate electrode is formed on the semiconductor base material SB located in the first region 1Ba of the bulk region 1B and on which the epitaxial growth treatment is performed via the second gate insulating film, and a third gate electrode is formed on the semiconductor base material SB located in the second region 1Bb of the bulk region 1B and on which the epitaxial growth treatment is not performed via the third gate insulating film.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shibun Tsuda
  • Patent number: 11068425
    Abstract: A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Hiraki, Sho Yamanaka
  • Patent number: 11068330
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Ota, Kan Takeuchi, Fumio Tsuchiya, Masaki Shimada, Shinya Konishi, Daisuke Oshida
  • Patent number: 11063055
    Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 11058360
    Abstract: It is possible to measure a pulse rate correctly, when a body moves. A frequency analysis unit 13 generates a pulse wave frequency signal by converting pulse wave detection signals detected by a light sensor 20 into a frequency domain signal from time domain signals. A body motion level determination unit 14 determines a body motion level of a subject based on acceleration detection signals output by an accelerometer 21. A peak detection unit 15 detects a peak of spectrum intensity in the pulse wave frequency signal within a peak searching range, which varies depending on the determined body motion level. A pulse calculation processing unit 16 generates pulse information based on a frequency position of the peak detected by the peak detection unit 15.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: July 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaki Jinnouchi
  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Patent number: 11062938
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 11056450
    Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: July 6, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuo Tomita