Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10726878
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 10725512
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
  • Patent number: 10727179
    Abstract: In order to easily sort failures due to short circuit between wires in an inductor, a semiconductor device includes a plurality of inductors (first inductor, second inductor) formed in a plurality of wiring layers. In each of the wiring layers, the metal layer of the first inductor and the metal layer of the second inductor respectively extend around the peripheral region from the inner periphery to the outer periphery in the same direction. The metal layer of the first inductor and the metal layer of the second inductor are arranged so as to be adjacent to each other.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Keiichiro Tanaka
  • Patent number: 10725880
    Abstract: There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shohei Matsukawa
  • Patent number: 10727863
    Abstract: An object of the present invention is to efficiently compress a plurality of kinds of data series with different sampling rates. A data compression device has a grouping unit and a compression unit. The grouping unit groups a plurality of kinds of data series with different sampling rates. The compression unit compresses the data series grouped by the grouping unit.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hirofumi Saito
  • Patent number: 10727542
    Abstract: A connector of a battery device includes a first terminal and a second terminal. The first terminal is coupleable to an opposed unit through a cable in a first state. The second terminal is coupleable to the opposed unit through the cable in the second state which is inverted upside down from the first state. A control device of the battery device is configured to charge the battery device with electric power from the opposed unit, when it is coupled to the opposed unit through the cable in the first state, and to supply the opposed unit with electric power from the battery device, when it is coupled to the opposed unit through the cable in the second state.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hajime Nozaki
  • Patent number: 10728428
    Abstract: A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Takitsune, Kazunori Masaki, Motoshige Ikeda
  • Patent number: 10719615
    Abstract: To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory that has a secret area where secret information is stored, an authentication controller that authenticates access to the nonvolatile memory, a flag information storage unit that stores flag information, and a memory controller that controls access to the nonvolatile memory by using the flag information stored in the flag information storage unit. The memory controller allows reading of the secret information from the secret area when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiko Asai, Takashi Kurafuji, Yoko Kimura
  • Patent number: 10721055
    Abstract: The sampling data signal and the sampling synchronizing clock are generated by sampling the data signal and the synchronizing clock, and the first driving pulse signal and the second driving pulse signal are generated based on the sampling data signal and the sampling synchronizing clock, and the isolator is driven by the first driving pulse signal and the second driving pulse signal.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuji Ikeda
  • Patent number: 10720780
    Abstract: A battery authentication system includes a battery pack, and a host device connected to the battery pack to charge the battery pack. The battery pack includes a battery, a discharge switch that turns on and off discharging of the battery, a charge switch that turns on and off charging of the battery, and a control integrated circuit (IC) that controls the battery. The control IC includes a charge/discharge control circuit that controls the discharge switch and the charge switch, and an authentication circuit that performs a process for performing an authentication with the host device. The authentication circuit is configured to perform a process associated with a first authentication. The charge/discharge control circuit is configured to control the discharge switch to be turned on when the first authentication is established. The authentication circuit is configured to perform a process associated with a second authentication.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayoshi Okawa, Hiromasa Takahashi
  • Patent number: 10719440
    Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keisuke Matsumoto, Seiji Mochizuki, Hiroshi Ueda, Katsushige Matsubara
  • Patent number: 10720203
    Abstract: A semiconductor device is provided that operates at improved write speeds without an increase in area. The semiconductor device according to the invention includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines provided to each row of the memory cells, a plurality of bit line pairs provided to each column of the memory cells, sense amplifiers that amplify the potential difference in the bit line pairs, data line pairs that transfer data to the bit line pairs, column selection circuits that permit receiving the data from the data line pairs, a column decoder that transmits column selection signals to the column selection circuits, and a sense amplifier control circuit that activates the sense amplifiers after the column decoder transmits the column selection signals to the column selection circuits.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Masahiro Yoshida
  • Patent number: 10720411
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 10718823
    Abstract: A device for open load diagnosis of a signal line in a digital system in which a logic state is represented by a band of voltages lying between first and second voltage limits is described. The device is configured to cause the signal line to reach a first, stable voltage lying in the band, to apply a second, different voltage to the signal line lying in the band and without leaving the band, to perform a time constant dependent measurement so as to determine a value of a parameter which is or depends on resistance of a load between the signal line and a reference line, to compare the value of the parameter with a reference value of the parameter and, in dependence on comparison, to signal the result.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hans-Juergen Braun
  • Patent number: 10714330
    Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 14, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoo Nakayama, Tatsuya Usami
  • Patent number: 10712803
    Abstract: To start power supply at a high current without applying USB Power Delivery, a power supply system includes a power supply device having a first USB connector conforming to the USB Type-C standard, and a power receiving device having a second USB connector conforming to the USB Type-C standard. The second USB connector includes a high current notification pin for notifying that it is possible to receive power at a high current greater than a predetermined reference current. When the second USB connector is coupled to the first USB connector, the power receiving device notifies the power supply device of the fact that it is possible to receive power at a high current greater than the predetermined reference current, through the high current notification pin. When receiving the notification, the power supply device determines that it is possible to start power supply to the receiving device at a high current.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satomi Suganuma
  • Patent number: 10714415
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 10706902
    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10708064
    Abstract: To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature. A signature verification unit performs signature verification by using the public key and the signature acquired by the acquiring unit, before the program acquired by the acquiring unit is booted. A calculation unit calculates a first MAC value by using a device eigenvalue and stores the first MAC value, when the result of signature verification by the signature verification unit is appropriate. A boot unit calculates a second MAC value by using the device eigenvalue, compares the second MAC value and the stored first MAC value with each other to determine that the program is legitimate, and executes boot based on the determination result.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seishiro Nagano, Shigenori Miyauchi
  • Patent number: 10705143
    Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka