Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11375353
    Abstract: A radio communication device includes an application execution unit which generates first transmission data including first application identification information, a communication unit which receives a message including first reception data including the first application identification information, and an occupancy rate determination unit including a transmission ID number counter which counts the number of first application identification information included in the first transmission data and which outputs a count result as a first transmission ID count value, a reception ID number counter which counts the number of first application identification information included in the first reception data and which outputs a count result as a first reception ID count value, and a comparison unit which compares the first transmission ID count value with the first reception ID count value to determine the number of transmission data and the number of reception data have a predetermined ratio.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 28, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Suguru Fujita, Hiroshi Chano
  • Patent number: 11373700
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 28, 2022
    Assignee: Renesas Electronics Corporation
    Inventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
  • Patent number: 11367238
    Abstract: An image processing device includes a three-dimensional graphics processor that generates three-dimensional drawing data based on a three-dimensional drawing command, a command converter that converts the three-dimensional drawing command into a two-dimensional drawing command, a two-dimensional graphics processor that generates two-dimensional drawing data based on the converted two-dimensional drawing command and a display controller that displays the two-dimensional drawing data in place of the three-dimensional drawing data when a load of the three-dimensional graphics processor is high.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 21, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiki Azuma, Shinya Tomari
  • Patent number: 11362207
    Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: June 14, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Sakai, Satoru Tokuda, Ryuuji Umemoto, Katsumi Eikyu, Hiroshi Yanagigawa
  • Patent number: 11358546
    Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 14, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayuki Daito
  • Patent number: 11360529
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 14, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
  • Patent number: 11360234
    Abstract: The present invention provides an electrode device, semiconductor device and a semiconductor system capable of accuracy detecting an object to be detected. According to one embodiment, the electrode device 11 is used for detecting the capacitance of the mutual capacitance system, and includes a reception electrode PR1, a transmission electrode PX1 arranged to face the reception electrode PR1, a transmission electrode PX2 arranged to face the reception electrode PR1 with the transmission electrode PX1 interposed therebetween, and a dielectric board 101 provided between the transmission electrode PX1 and the transmission electrode PX2 to fix the distance and the dielectric constant between the transmission electrode PX1 and the transmission electrode PX2.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 14, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya Mizokami, Masahiro Araki
  • Patent number: 11356063
    Abstract: Amplification device and processes capable of miniaturization in a device for performing linear amplification and switching amplification operations on incoming signals are provided. The amplifying device includes a first amplifying unit for amplifying an input signal and outputting a first output signal, the input switch unit connected in parallel with the first amplifying unit for performing a switching operation by an input signal and outputting a switch output signal, and a second amplifying unit for amplifying a first output signal or a switch output signal and outputting a second output signal, and the first amplifying unit or the input switch unit operates based on the type of the input signal.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 7, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya Ito, Tomoumi Yagasaki
  • Patent number: 11352048
    Abstract: A rotation detection device includes a rotation detection circuit, a step-up power supply circuit, a step-down power supply circuit, a first power supply path, and a second power supply path. The rotation detection circuit is configured to detect a rotation number of a motor that generates a torque applied to a steering mechanism of a vehicle, based on an electric signal. The electric signal is generated according to a rotation angle of the motor that is acquired through an in-vehicle sensor.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 7, 2022
    Assignees: JTEKT CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Kozuka, Masato Oda, Tadashi Kawahara, Masashi Oki
  • Patent number: 11347964
    Abstract: A hardware circuit in which integer numbers are used to represent fixed-point numbers having an integer part and a fractional part is disclosed. The hardware circuit comprises a multiply-accumulate unit configured to perform convolution operations using input data and weights and, in dependence thereon, to generate an intermediate result. The hardware circuit comprises a bias bit shifter configured to shift a bias value bitwise by a bias shift value so as to provide a bit-shifted bias value, a carry bit shifter configured to shift a carry value bitwise by a carry shift value so as to provide a bit-shifted carry value, an adder tree configured to add the intermediate result, the bit-shifted bias value and the bit-shifted carry value so as to provide a multiple-accumulate result and a multiply-accumulate bit shifter configured to shift the multiple-accumulate result bitwise by a multiply-accumulate shift value) to provide a bit-shifted multiply-accumulate result.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 31, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Matthias Nahr
  • Patent number: 11342450
    Abstract: A semiconductor device having an IE-type IGBT structure comprises a stripe-shaped trench gate and a stripe-shaped trench emitter arranged to face the trench gate formed in a semiconductor substrate. The semiconductor device further comprises an N-type emitter layer and a P-type base layer both surrounded by the trench gate and the trench emitter formed in the semiconductor substrate. The semiconductor device also comprises a P-type base contact layer arranged on one side of the trench emitter and formed in the semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrode. The trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 24, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 11342430
    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 24, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Digh Hisamoto, Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 11335702
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, a ferroelectric film, a first seed layer and a control gate electrode. The semiconductor substrate includes a source region and a drain region which are formed on a main surface of the semiconductor substrate. The insulating film is formed on the main surface of the semiconductor substrate such that the insulating film is positioned between the source region and the drain region in a plan view. The ferroelectric film is formed on the insulating film and includes hafnium and oxygen. The first seed layer is formed on the ferroelectric film. The control gate electrode is formed on the ferroelectric film. A material of the first seed layer includes at least one material of the ferroelectric film and at least one material of the first conductive film.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 17, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tadashi Yamaguchi
  • Patent number: 11333716
    Abstract: To make an excessive power receiving request by a sink when a USB Type-C legacy cable is used. An electronic device includes a first and second terminals connected to a cable, a detection circuit for detecting the voltage of the first and second terminals, and a first or second terminal detected by the detection circuit. It is provided with a controller that determines the type of cable based on the terminal voltage and confirms the power supply capacity of the external electronic device connected via the cable according to the type of cable.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: May 17, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayuki Suzuki
  • Patent number: 11335571
    Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 17, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Tsuchiya, Akira Matsumoto
  • Patent number: 11329152
    Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 10, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Takahiro Mori, Yuji Ishii
  • Patent number: 11327830
    Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 10, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kimihiko Nakazawa, Takahiro Irita
  • Patent number: 11322668
    Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 3, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigo Namioka, Yasutaka Nakashiba
  • Publication number: 20220121442
    Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Sugako OHTANI, Hiroyuki KONDO
  • Patent number: 11307479
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba