Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: Methods and apparatus for sharing network bandwidth between devices connected to a bus are presented. Each of the devices belongs to one of a number of device classes. Each device class is associated with a respective data transfer rate at which information may be exchanged over the bus. An exemplary method includes the step of assigning a gap interval to each device based on at least the data transfer rate of the class to which the device belongs, the assigned gap interval being inserted between portions of a data stream sent by the corresponding device over the bus. The assigned gap interval may be inserted between portions of a data stream sent by the corresponding device over the bus to achieve the desired data rate resulting in an equitable sharing of bandwidth between the devices connected to the bus.

Abstract: To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.

Abstract: A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: A method of forming a pattern including a first pattern portion having a first minimum dimension and a second pattern portion having a second minimum dimension includes a first exposure step of performing exposure using a Levenson-type mask and a second exposure step of performing exposure using a half tone-type mask. When second minimum dimension is 1.3 time or more than the first minimum dimension, the exposure amount of the second exposure step is set to be equal to or smaller than the exposure amount of the first exposure step.

Abstract: Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed. For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: There is provided a display driver device (liquid crystal driver) causing no degradation in display image quality even when a plurality of signal lines (source lines) of a display panel are divided into a plurality of groups as a countermeasure against EMI. With a liquid crystal display driver device (the liquid crystal driver) for generating image signals to be impressed to respective signal lines of a display panel upon receiving display image data, and outputting the image signals in a lump, corresponding to every one line, according to an output timing signal inputted from outside, output amplifiers, in the last stage of the liquid crystal driver, for outputting the image signals, respectively, are divided into a plurality of groups, and the output amplifiers of respective groups are caused to undergo a periodical change in output sequence while the respective image signals are slightly staggered in output timing by the group.

Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

Abstract: The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0?b?a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened.

Abstract: There is a need for turning off a transistor in a power supply switch circuit irrespective of relative potential relationship between a contact power supply terminal and an internal power supply line and making it possible to decrease an on-resistance of an MOS transistor without increasing the size of the MOS transistor constituting the power supply switch circuit. The power supply switch circuit is comprised of two PMOS transistors whose gate terminals connect with two pull-up circuits. A charge pump circuit generates a negative voltage and is connected to a pull-down circuit. The pull-down circuit is connected to the gate terminals in common. During a contactless operation, the pull-up circuit short-circuits one gate terminal to a contact power supply terminal VDD and the other gate terminal to an internal power supply line VDDA. During a contact operation, the pull-up circuit supplies both gate terminals with a negative voltage from the charge pump circuit.