Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.

Abstract: A method can include obtaining a voltage across a first transistor as an obtained voltage. The method can also include multiplying the obtained voltage by a predetermined multiple M to yield a multiplied voltage. The method can further include applying the multiplied voltage to a second transistor, wherein the second transistor is N times smaller than the first transistor. The method can additionally include providing an output current of the second transistor as an M/N scaled estimate of an output current of the first transistor.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: The present invention relates generally to integrated circuit (IC) fabrication processes. The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer. The present invention further relates to a high-k gate obtainable by a method of the invention.

Abstract: In a reception apparatus, a matched filter that has conventionally been arranged in a searcher unit is mounted on an acquisition unit together with a large scale memory. The large scale memory once stores reception chip signals, and thereafter outputs them to the matched filter and to the delay profile calculation unit. A setting register receives an acquisition signal and outputs it to the matched filter. The matched filter performs acquisition of the reception chip signals outputted from the large scale memory, and outputs a despread timing signal to a despread circuit, a code generation circuit and the delay profile calculation unit.

Abstract: A method of determining defects in photomasks according to the present invention is designed to increase the yield of the manufacture of photomasks and to decrease the cost of inspecting the photomasks. In the method, circuit data 1 representing a circuit to be formed on a semiconductor substrate by photolithography is prepared, and layout data 2 is prepared from the circuit data 1. The layout data is converted to compensated layout data by performing RET. Further, mask-manufacturing data is developed from the compensated layout data. To form patterns on a semiconductor substrate by photolithography, attribute information is imparted to the mask-manufacturing data. The attribute information represents whether the patterns are adaptive to electrically active regions or electrically non-active region. In the mask-inspecting process 6, a criterion for determining whether the patterns formed on the photomasks have defects is changed in accordance with the attribute information.

Abstract: A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the switch is turned off, a switch connected to a charge supply unit is turned on while the potential is rising, so that the charge supply unit is electrically coupled to the pseudo-ground line. Thereby, charges accumulated in the charge supply unit are discharged to the pseudo-ground line. The switch is turned off to decouple electrically the charge supply unit from the pseudo-ground line. Thereby, when the power supply is interrupted, a part of the charges for raising the potential of the pseudo-ground line is supplemented with the charges of the charge supply unit.

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.

Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: An IC provided in an optical disk device having an objective lens and a pickup for a disk. The IC has a circuit for holding a signal which drives the objective lens in a focus or tracking direction and for detecting the moving direction of the objective lens, and a circuit for generating a signal which applies an acceleration to the objective lens. When the objective lens passes through a defect on the disk, on the basis of the detected moving direction of the objective lens, the IC applies the acceleration alternately in plus and minus directions to the objective lens to make the objective lens stationary. As a result, after the defect passage, the objective lens can be quickly returned to a focused point or an on-track position and reproducing/recording operation can be resumed.

Abstract: An apparatus, in one embodiment, can include a configuration including a plurality of heat generation devices. The apparatus also includes a plurality of thermal sensors respectively, operably connected to each of the plurality of heat generation devices, wherein each thermal sensor of the plurality of thermal sensors includes a respective output terminal configured to provide a voltage representative of the temperature of the respective heat generation device. The apparatus further includes an output circuit configured to output the highest temperature information among the heat generation devices. The output terminals of the plurality of thermal sensors are tied together. A corresponding method is also discussed.

Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.

Abstract: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.