Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Abstract: The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.

Abstract: A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CD0 and CD1, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #2, the data of Bank 2 stored in CD1, Row 2 cannot be written back since Bank 2 is busy with the cycle #1, the data of Bank 0 stored in CD 0, Row 2 can be written back instead.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract: A method of simplifying the arithmetic operation in a global motion compensation process approximates the motion vector field of the whole image without using many parameters. Motion vectors in the global motion compensation are found by the interpolation and/or extrapolation of the motion vectors of a plurality of representative points 602, 603 and 604 having particular features in the spatial distance thereof. Since the shift operation can be substituted for the division for synthesizing a predicted image of global motion compensation, the processing using a computer or a dedicated hardware is simplified.

Abstract: An IC card module includes first external connecting terminals and second external connecting terminals both exposed to one surface of a card substrate, a microcomputer connected to the first external connecting terminals, a memory controller connected to the second external connecting terminals, and a volatile memory connected to the memory controller. The shape of the card substrate and the layout of the first external connecting terminals are based on a standard of plug-in UICC of ETSI TS 102 221 V4.4.0 (2001-10). The second external connecting terminals are disposed outside the minimum range of the terminal layout based on the standard for the first external connecting terminals. The first and second external connecting terminals include signal terminals electrically separated from one another.

Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: A current source block and a negative resistance generation block are connected in parallel. The negative resistance generation block generates a negative resistance in response to the minute variations of an output voltage. Thus the output resistance of a current source circuit is given by the combined resistance of the negative resistance and the resistance of a resistor in the current source block connected in parallel. The resistance of the resistor in the current source block and the negative resistance are controlled to be substantially the same to thereby increase the output resistance of the current source circuit. The current source circuit serves to increase an output resistance when viewed from an differential output terminal. As a result, use of this current source circuit realizes a differential amplifier providing a high gain.

Abstract: A three-phase DC motor output stage including a predriver that supplies drive voltages to power MOSFETs supplies output voltages to three-phase coils, monitors whether each of gate-to-source voltages of the power MOSFETs is greater than or equal to a predetermined voltage and thereby detects a current zero cross, and employs the output of such current zero cross detection in PLL control for controlling energization switching timing and thereby forms drive voltages of 180-degree energization. Lower hooks with a voltage minimum phase as GND and upper hooks with a voltage maximum phase as a source are set as patterns alternately repeated for every electrical angle of 60 degrees. The patterns are expressed in linear approximation to generate sine wave-like drive voltages, thereby causing sine wave-like currents to flow into the three-phase coils.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: There is a need for providing a variable amplifier circuit suited for a semiconductor integrated circuit and a high-performance camera preprocessing LSI using the variable amplifier circuit. At first timing, a first input capacitor acquires a first signal. An amplifier circuit amplifies a second signal acquired to the second input capacitor according to a gain corresponding to a capacity ratio between the second input capacitor and a feedback capacitor composed of a variable capacitor device. At second timing, the second input capacitor acquires a second signal. The amplifier circuit amplifies the first signal according to a gain corresponding to a capacity ratio between the first input capacitor and the feedback capacitor. A variable gain amplifier circuit interleavingly amplifies the first signal and the second signal in synchronization with the first timing and the second timing.

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.