Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a power supply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.

Abstract: To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.

Abstract: A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.

Abstract: A multimode wireless terminal suitable for received level monitoring for a base station serving as an intersystem handover destination includes a first wireless transmitter-receiver unit for GSM, a second wireless transmitter-receiver unit for WCDMA, and a communication processor unit and an antenna switch unit connected to these wireless transmitter-receiver units. While conducting communication with a WCDMA network system via the second wireless transmitter-receiver unit, a level of a signal received from a GSM base station is monitored via the first wireless transmitter-receiver unit. A communication processor unit determines whether the level monitoring is interfered with by a WCDMA transmission signal, on the basis of a relation between a WCDMA transmission frequency and a reception frequency supplied from the GSM base station.

Abstract: In one aspect of the present invention, a memory device comprises an interface which interfaces with an external device, an IC chip which stores one or more application programs and executes the application programs, a memory which stores associated data associated with the one or more application programs, and a controller connected with the interface, the IC chip, and the memory. In response to a predetermined command received from the external device by way of the interface, the controller performs transfer of the associated data between the IC chip and the memory without passing the associated data to the host device during transfer of the associated data between the IC chip and the memory.

Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.

Abstract: A memory cell of a SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly consist of a square pole laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: In a PLL circuit including an oscillator, a phase comparator, a charge pump circuit, and a loop filter, without providing a plurality of capacitative elements, that is, without increasing the occupied area so much, the characteristics of the PLL circuit can be adjusted according to manufacture variations in a resistive element and a capacitative element, and a loop filter can be formed on a chip. A resistive element and a capacitative element of a loop filter are formed on a semiconductor chip. As the resistive element, a plurality of elements having different resistance values are provided and switched by a switch, thereby enabling the resistance value to be adjusted. Current in a charge pump circuit is also made adjustable, and the current of the charge pump circuit is adjusted according to switching among the resistance values of the resistive elements.

Abstract: In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.

Abstract: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

Abstract: A production method of a semiconductor device which includes the steps of exposing a resist coated on a substrate of a semiconductor device by projecting a first light pattern on the substrate of the semiconductor device the first light pattern being formed by passing light through a first mask, and exposing the resist by projecting a second light pattern on the substrate, the second light pattern being formed by passing light through a second mask. In the step of exposing the resist by projecting the second light pattern, the second light pattern is formed by excimer laser light having an annular shape and passed through the second mask.

Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.