Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.

Abstract: This invention is to provide an ultra-miniaturized, thin-sized memory card provided with a mechanism for preventing a wrong insertion to a memory card slot. A multi-function memory card is composed of a card body and a cap for housing the card body. The card body is made of mold resin that encapsulates plural semiconductor chips mounted on a main surface of a wiring substrate. The card body is housed into the cap with the back face of the wiring substrate facing outward. Guide channels are provided at both side faces of the cap for preventing that the card is inserted upside down. Further, a convex section is provided at the trailing edge of the cap for preventing that the card is inserted in the wrong direction.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: A BGA type semiconductor device which realizes its high speed operation and high integration density by shortening power supply or grounding wires to reduce its inductance. In the BGA type semiconductor device, the power supply or grounding wires are provided in the vicinity of the center of a BGA board to realize the high-speed operation and high integration density, whereby an electronic circuit or equipment using the BGA type semiconductor device can be made high in operational speed and made sophisticated in function.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.

Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Abstract: A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage-OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: A connection method is disclosed for a high-performance semiconductor system. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. Semiconductor chips and the interposer chips are polished by grinding at their rear surfaces, holes are formed at rear surface positions corresponding to external electrode parts on the device side (front surface side) so that the holes extend to front surface electrodes, and metal plating films are applied to the side walls of the holes and rear surface side. Metal bumps of another semiconductor chip laminated at an upper stage being press-fitted into the holes applied with the metal plating films through deformation and being geometrically calked in the through holes formed in the semiconductor chip so as to electrically connected thereto.

Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.

Abstract: Disclosed herein is an encryption and decryption communication semiconductor device comprising at least, a communication interface for performing a transfer of data according to a predetermined communication system, one or two or more encryption/decryption circuits which encrypt or decrypt input data in accordance with a predetermined algorithm, and a plurality of external interfaces for performing the input/output of data from and to external devices. The communication interface, the encryption/decryption circuits and the plurality of external interfaces are formed on one semiconductor chip. In the cryption and decryption communication semiconductor device, input data sent from any one of the plurality of external interfaces is encrypted or decrypted by at least one of the encryption/decryption circuits and is capable of being outputted to any different one of the plurality of external interfaces.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: The present invention provides a communication semiconductor integrated circuit device equipped with a high-frequency power amplifier circuit including a gain control amplifier and a bias circuit which supplies such a bias current as to linearly change the gain of the gain control amplifier, and a wireless communication system using the same. A bias current generating circuit which supplies a bias current to a linear amplifier that constitutes the communication high-frequency power amplifier circuit, comprises a plurality of variable current sources respectively different in current value and start level. These variable current sources are controlled according to an input control voltage and thereby combine their currents into a bias current. The combined bias current changes exponentially with respect to the input control voltage.