Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.

Abstract: With a fluid insulating material applied on a convex substrate and a fluid insulating material applied on a concave substrate, a columnar conductive portion of the convex substrate is inserted into a hole of the concave substrate. With this, a conductive portion and an internal interconnection are electrically connected with each other via a bump. Therefore, a semiconductor device having a through electrode which enables a size reduction, has high reliability and is easily formed even with a large aspect ratio, and a method of manufacturing the same are obtained.

Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

Abstract: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.

Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Abstract: The present invention provides a one-chip microcomputer that can realize the control of cooling equipment, the control of the brightness of a display device, and the control of the charge and discharge of a battery without mounting an analog circuit. The one-chip microcomputer is used in a notebook-size personal computer, and comprises: a CPU that performs operation processing; a CPG that generates a clock signal; a flash memory that stores a control program; a RAM that sores data; an 8-bit timer that controls fans; and a 14-bit timer that controls an LCD brightness controller of an LCD and a voltage charger of batteries. The one-chip microcomputer controls the fans by the 8-bit timer without mounting the analog circuit and can adjust the LCD brightness by the 14-bit timer.

Abstract: A semiconductor device comprising a high-dielectric film in a part of a gate insulation film is provided by a more simplified method. In a semiconductor device having a first region and a second region, a first gate electrode, a second gate electrode and a high-dielectric gate insulation film are formed in the first region (core part). The first gate electrode and the second gate electrode have different composition ratios. The first gate electrode and the second gate electrode are formed on the high-dielectric gate insulation film. Furthermore, a third gate electrode and a fourth gate electrode and a SiON film or SiO2 film are formed in the second region (I/O part). Impurity elements doped in the third gate electrode and the fourth gate electrode are different in kind and/or concentration. In addition, the third gate electrode and the fourth gate electrode are formed on the SiON film or SiO2 film.

Abstract: A first opening portion for via hole opening is formed above an electrode groove and a second opening portion for via hole opening for connecting with wiring layer is formed on interlayer insulation film at a position corresponding to the top portion of wiring layer provided out of a capacitor formation area. At this time, the diameter of the opening of the first opening portion is set larger than the second opening portion. If the diameter of the second opening portion is 0.36 ?m, the diameter of the opening of the first opening portion is set to 0.38 ?m.

Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

Abstract: A card device has a regulator (5), a first internal circuit (6) and a second internal circuit (7), and the regulator supplies, to the second internal circuit, an internal voltage generated by dropping an external voltage (VCC) when the external voltage is high, and exactly supplies the external voltage as the internal voltage to the second internal circuit when the external voltage is low, and the external voltage is supplied as an operating power source to the first internal circuit and a transition to a low consumed power state is carried out if a command is not input for a certain period. The card device stops the operation of the regulator and suppresses the supply of the internal voltage to the second internal circuit in the transition to the low consumed power state. In the low consumed power state, consequently, it is possible to suppress a power consumption in each of the regulator and the second internal circuit in the card device.

Abstract: When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals ?1 and ?2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals ?1 and ?2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

Abstract: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).

Abstract: A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.

Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.